NXP Semiconductors
K32L2B31A
2024.06.02
K32L2B31A NXP Microcontroller
CM0PLUS
r0p0
little
2
false
8
32
ADC0
Analog-to-Digital Converter
ADC0
0x0
0x0
0x70
registers
n
ADC0
15
CFG1
ADC Configuration Register 1
0x8
32
read-write
n
0x0
0x0
ADICLK
Input Clock Select
0
2
read-write
00
Bus clock
#00
01
Bus clock divided by 2(BUSCLK/2)
#01
10
Alternate clock (ALTCLK)
#10
11
Asynchronous clock (ADACK)
#11
ADIV
Clock Divide Select
5
2
read-write
00
The divide ratio is 1 and the clock rate is input clock.
#00
01
The divide ratio is 2 and the clock rate is (input clock)/2.
#01
10
The divide ratio is 4 and the clock rate is (input clock)/4.
#10
11
The divide ratio is 8 and the clock rate is (input clock)/8.
#11
ADLPC
Low-Power Configuration
7
1
read-write
0
Normal power configuration.
#0
1
Low-power configuration. The power is reduced at the expense of maximum clock speed.
#1
ADLSMP
Sample Time Configuration
4
1
read-write
0
Short sample time.
#0
1
Long sample time.
#1
MODE
Conversion mode selection
2
2
read-write
00
When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output.
#00
01
When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output.
#01
10
When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output
#10
11
When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output
#11
CFG2
ADC Configuration Register 2
0xC
32
read-write
n
0x0
0x0
ADACKEN
Asynchronous Clock Output Enable
3
1
read-write
0
Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.
#0
1
Asynchronous clock and clock output is enabled regardless of the state of the ADC.
#1
ADHSC
High-Speed Configuration
2
1
read-write
0
Normal conversion sequence selected.
#0
1
High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
#1
ADLSTS
Long Sample Time Select
0
2
read-write
00
Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
#00
01
12 extra ADCK cycles; 16 ADCK cycles total sample time.
#01
10
6 extra ADCK cycles; 10 ADCK cycles total sample time.
#10
11
2 extra ADCK cycles; 6 ADCK cycles total sample time.
#11
MUXSEL
ADC Mux Select
4
1
read-write
0
ADxxa channels are selected.
#0
1
ADxxb channels are selected.
#1
CLM0
ADC Minus-Side General Calibration Value Register
0x6C
32
read-write
n
0x0
0x0
CLM0
Calibration Value
0
6
read-write
CLM1
ADC Minus-Side General Calibration Value Register
0x68
32
read-write
n
0x0
0x0
CLM1
Calibration Value
0
7
read-write
CLM2
ADC Minus-Side General Calibration Value Register
0x64
32
read-write
n
0x0
0x0
CLM2
Calibration Value
0
8
read-write
CLM3
ADC Minus-Side General Calibration Value Register
0x60
32
read-write
n
0x0
0x0
CLM3
Calibration Value
0
9
read-write
CLM4
ADC Minus-Side General Calibration Value Register
0x5C
32
read-write
n
0x0
0x0
CLM4
Calibration Value
0
10
read-write
CLMD
ADC Minus-Side General Calibration Value Register
0x54
32
read-write
n
0x0
0x0
CLMD
Calibration Value
0
6
read-write
CLMS
ADC Minus-Side General Calibration Value Register
0x58
32
read-write
n
0x0
0x0
CLMS
Calibration Value
0
6
read-write
CLP0
ADC Plus-Side General Calibration Value Register
0x4C
32
read-write
n
0x0
0x0
CLP0
Calibration Value
0
6
read-write
CLP1
ADC Plus-Side General Calibration Value Register
0x48
32
read-write
n
0x0
0x0
CLP1
Calibration Value
0
7
read-write
CLP2
ADC Plus-Side General Calibration Value Register
0x44
32
read-write
n
0x0
0x0
CLP2
Calibration Value
0
8
read-write
CLP3
ADC Plus-Side General Calibration Value Register
0x40
32
read-write
n
0x0
0x0
CLP3
Calibration Value
0
9
read-write
CLP4
ADC Plus-Side General Calibration Value Register
0x3C
32
read-write
n
0x0
0x0
CLP4
Calibration Value
0
10
read-write
CLPD
ADC Plus-Side General Calibration Value Register
0x34
32
read-write
n
0x0
0x0
CLPD
Calibration Value
0
6
read-write
CLPS
ADC Plus-Side General Calibration Value Register
0x38
32
read-write
n
0x0
0x0
CLPS
Calibration Value
0
6
read-write
CV1
Compare Value Registers
0x30
32
read-write
n
0x0
0x0
CV
Compare Value.
0
16
read-write
CV2
Compare Value Registers
0x4C
32
read-write
n
0x0
0x0
CV
Compare Value.
0
16
read-write
MG
ADC Minus-Side Gain Register
0x30
32
read-write
n
0x0
0x0
MG
Minus-Side Gain
0
16
read-write
OFS
ADC Offset Correction Register
0x28
32
read-write
n
0x0
0x0
OFS
Offset Error Correction Value
0
16
read-write
PG
ADC Plus-Side Gain Register
0x2C
32
read-write
n
0x0
0x0
PG
Plus-Side Gain
0
16
read-write
RA
ADC Data Result Register
0x20
32
read-only
n
0x0
0x0
D
Data result
0
16
read-only
RB
ADC Data Result Register
0x34
32
read-only
n
0x0
0x0
D
Data result
0
16
read-only
SC1A
ADC Status and Control Registers 1
0x0
32
read-write
n
0x0
0x0
ADCH
Input channel select
0
5
read-write
00000
When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
#00000
00001
When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
#00001
00010
When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
#00010
00011
When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
#00011
00100
When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
#00100
00101
When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
#00101
00110
When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
#00110
00111
When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
#00111
01000
When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
#01000
01001
When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
#01001
01010
When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
#01010
01011
When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
#01011
01100
When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
#01100
01101
When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
#01101
01110
When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
#01110
01111
When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
#01111
10000
When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
#10000
10001
When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
#10001
10010
When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
#10010
10011
When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
#10011
10100
When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
#10100
10101
When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
#10101
10110
When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
#10110
10111
When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
#10111
11010
When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.
#11010
11011
When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.
#11011
11101
When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
#11101
11110
When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
#11110
11111
Module is disabled.
#11111
AIEN
Interrupt Enable
6
1
read-write
0
Conversion complete interrupt is disabled.
#0
1
Conversion complete interrupt is enabled.
#1
COCO
Conversion Complete Flag
7
1
read-only
0
Conversion is not completed.
#0
1
Conversion is completed.
#1
DIFF
Differential Mode Enable
5
1
read-write
0
Single-ended conversions and input channels are selected.
#0
1
Differential conversions and input channels are selected.
#1
SC1B
ADC Status and Control Registers 1
0x4
32
read-write
n
0x0
0x0
ADCH
Input channel select
0
5
read-write
00000
When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
#00000
00001
When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
#00001
00010
When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
#00010
00011
When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
#00011
00100
When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
#00100
00101
When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
#00101
00110
When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
#00110
00111
When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
#00111
01000
When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
#01000
01001
When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
#01001
01010
When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
#01010
01011
When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
#01011
01100
When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
#01100
01101
When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
#01101
01110
When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
#01110
01111
When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
#01111
10000
When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
#10000
10001
When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
#10001
10010
When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
#10010
10011
When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
#10011
10100
When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
#10100
10101
When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
#10101
10110
When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
#10110
10111
When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
#10111
11010
When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.
#11010
11011
When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.
#11011
11101
When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
#11101
11110
When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
#11110
11111
Module is disabled.
#11111
AIEN
Interrupt Enable
6
1
read-write
0
Conversion complete interrupt is disabled.
#0
1
Conversion complete interrupt is enabled.
#1
COCO
Conversion Complete Flag
7
1
read-only
0
Conversion is not completed.
#0
1
Conversion is completed.
#1
DIFF
Differential Mode Enable
5
1
read-write
0
Single-ended conversions and input channels are selected.
#0
1
Differential conversions and input channels are selected.
#1
SC2
Status and Control Register 2
0x20
32
read-write
n
0x0
0x0
ACFE
Compare Function Enable
5
1
read-write
0
Compare function disabled.
#0
1
Compare function enabled.
#1
ACFGT
Compare Function Greater Than Enable
4
1
read-write
0
Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.
#0
1
Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.
#1
ACREN
Compare Function Range Enable
3
1
read-write
0
Range function disabled. Only CV1 is compared.
#0
1
Range function enabled. Both CV1 and CV2 are compared.
#1
ADACT
Conversion Active
7
1
read-only
0
Conversion not in progress.
#0
1
Conversion in progress.
#1
ADTRG
Conversion Trigger Select
6
1
read-write
0
Software trigger selected.
#0
1
Hardware trigger selected.
#1
DMAEN
DMA Enable
2
1
read-write
0
DMA is disabled.
#0
1
DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.
#1
REFSEL
Voltage Reference Selection
0
2
read-write
0
Default voltage reference pin pair, that is, external pins VREFH and VREFL
#00
1
Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU
#01
SC3
Status and Control Register 3
0x24
32
read-write
n
0x0
0x0
ADCO
Continuous Conversion Enable
3
1
read-write
0
One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
#0
1
Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
#1
AVGE
Hardware Average Enable
2
1
read-write
0
Hardware average function disabled.
#0
1
Hardware average function enabled.
#1
AVGS
Hardware Average Select
0
2
read-write
00
4 samples averaged.
#00
01
8 samples averaged.
#01
10
16 samples averaged.
#10
11
32 samples averaged.
#11
CAL
Calibration
7
1
read-write
CALF
Calibration Failed Flag
6
1
read-write
0
Calibration completed normally.
#0
1
Calibration failed. ADC accuracy specifications are not guaranteed.
#1
CMP0
High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
CMP0
0x0
0x0
0x6
registers
n
CMP0
16
CR0
CMP Control Register 0
0x0
8
read-write
n
0x0
0x0
FILTER_CNT
Filter Sample Count
4
3
read-write
000
Filter is disabled. SE = 0, COUT = COUTA.
#000
001
One sample must agree. The comparator output is simply sampled.
#001
010
2 consecutive samples must agree.
#010
011
3 consecutive samples must agree.
#011
100
4 consecutive samples must agree.
#100
101
5 consecutive samples must agree.
#101
110
6 consecutive samples must agree.
#110
111
7 consecutive samples must agree.
#111
HYSTCTR
Comparator hard block hysteresis control
0
2
read-write
00
Level 0
#00
01
Level 1
#01
10
Level 2
#10
11
Level 3
#11
CR1
CMP Control Register 1
0x1
8
read-write
n
0x0
0x0
COS
Comparator Output Select
2
1
read-write
0
Set the filtered comparator output (CMPO) to equal COUT.
#0
1
Set the unfiltered comparator output (CMPO) to equal COUTA.
#1
EN
Comparator Module Enable
0
1
read-write
0
Analog Comparator is disabled.
#0
1
Analog Comparator is enabled.
#1
INV
Comparator INVERT
3
1
read-write
0
Does not invert the comparator output.
#0
1
Inverts the comparator output.
#1
OPE
Comparator Output Pin Enable
1
1
read-write
0
CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
#0
1
CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.
#1
PMODE
Power Mode Select
4
1
read-write
0
Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
#0
1
High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
#1
SE
Sample Enable
7
1
read-write
0
Sampling mode is not selected.
#0
1
Sampling mode is selected.
#1
TRIGM
Trigger Mode Enable
5
1
read-write
0
Trigger mode is disabled.
#0
1
Trigger mode is enabled.
#1
WE
Windowing Enable
6
1
read-write
0
Windowing mode is not selected.
#0
1
Windowing mode is selected.
#1
DACCR
DAC Control Register
0x4
8
read-write
n
0x0
0x0
DACEN
DAC Enable
7
1
read-write
0
DAC is disabled.
#0
1
DAC is enabled.
#1
VOSEL
DAC Output Voltage Select
0
6
read-write
VRSEL
Supply Voltage Reference Source Select
6
1
read-write
0
Vin1 is selected as resistor ladder network supply reference.
#0
1
Vin2 is selected as resistor ladder network supply reference.
#1
FPR
CMP Filter Period Register
0x2
8
read-write
n
0x0
0x0
FILT_PER
Filter Sample Period
0
8
read-write
MUXCR
MUX Control Register
0x5
8
read-write
n
0x0
0x0
MSEL
Minus Input Mux Control
0
3
read-write
000
IN0
#000
001
IN1
#001
010
IN2
#010
011
IN3
#011
100
IN4
#100
101
IN5
#101
110
IN6
#110
111
IN7
#111
PSEL
Plus Input Mux Control
3
3
read-write
000
IN0
#000
001
IN1
#001
010
IN2
#010
011
IN3
#011
100
IN4
#100
101
IN5
#101
110
IN6
#110
111
IN7
#111
PSTM
Pass Through Mode Enable
7
1
read-write
0
Pass Through Mode is disabled.
#0
1
Pass Through Mode is enabled.
#1
SCR
CMP Status and Control Register
0x3
8
read-write
n
0x0
0x0
CFF
Analog Comparator Flag Falling
1
1
read-write
0
Falling-edge on COUT has not been detected.
#0
1
Falling-edge on COUT has occurred.
#1
CFR
Analog Comparator Flag Rising
2
1
read-write
0
Rising-edge on COUT has not been detected.
#0
1
Rising-edge on COUT has occurred.
#1
COUT
Analog Comparator Output
0
1
read-only
DMAEN
DMA Enable Control
6
1
read-write
0
DMA is disabled.
#0
1
DMA is enabled.
#1
IEF
Comparator Interrupt Enable Falling
3
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
IER
Comparator Interrupt Enable Rising
4
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
DAC0
12-Bit Digital-to-Analog Converter
DAC0
0x0
0x0
0x24
registers
n
DAC0
25
C0
DAC Control Register
0x21
8
read-write
n
0x0
0x0
DACBBIEN
DAC Buffer Read Pointer Bottom Flag Interrupt Enable
0
1
read-write
0
The DAC buffer read pointer bottom flag interrupt is disabled.
#0
1
The DAC buffer read pointer bottom flag interrupt is enabled.
#1
DACBTIEN
DAC Buffer Read Pointer Top Flag Interrupt Enable
1
1
read-write
0
The DAC buffer read pointer top flag interrupt is disabled.
#0
1
The DAC buffer read pointer top flag interrupt is enabled.
#1
DACEN
DAC Enable
7
1
read-write
0
The DAC system is disabled.
#0
1
The DAC system is enabled.
#1
DACRFS
DAC Reference Select
6
1
read-write
0
The DAC selects DACREF_1 as the reference voltage.
#0
1
The DAC selects DACREF_2 as the reference voltage.
#1
DACSWTRG
DAC Software Trigger
4
1
read-write
0
The DAC soft trigger is not valid.
#0
1
The DAC soft trigger is valid.
#1
DACTRGSEL
DAC Trigger Select
5
1
read-write
0
The DAC hardware trigger is selected.
#0
1
The DAC software trigger is selected.
#1
LPEN
DAC Low Power Control
3
1
read-write
0
High-Power mode
#0
1
Low-Power mode
#1
C1
DAC Control Register 1
0x22
8
read-write
n
0x0
0x0
DACBFEN
DAC Buffer Enable
0
1
read-write
0
Buffer read pointer is disabled. The converted data is always the first word of the buffer.
#0
1
Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer.
#1
DACBFMD
DAC Buffer Work Mode Select
1
2
read-write
00
Normal mode
#00
10
One-Time Scan mode
#10
11
FIFO mode
#11
DMAEN
DMA Enable Select
7
1
read-write
0
DMA is disabled.
#0
1
DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.
#1
C2
DAC Control Register 2
0x23
8
read-write
n
0x0
0x0
DACBFRP
DAC Buffer Read Pointer
4
1
read-write
DACBFUP
DAC Buffer Upper Limit
0
1
read-write
DAT0H
DAC Data High Register
0x2
8
read-write
n
0x0
0x0
DATA1
DATA1
0
4
read-write
DAT0L
DAC Data Low Register
0x0
8
read-write
n
0x0
0x0
DATA0
DATA0
0
8
read-write
DAT1H
DAC Data High Register
0x5
8
read-write
n
0x0
0x0
DATA1
DATA1
0
4
read-write
DAT1L
DAC Data Low Register
0x2
8
read-write
n
0x0
0x0
DATA0
DATA0
0
8
read-write
SR
DAC Status Register
0x20
8
read-write
n
0x0
0x0
DACBFRPBF
DAC Buffer Read Pointer Bottom Position Flag
0
1
read-write
0
The DAC buffer read pointer is not equal to C2[DACBFUP].
#0
1
The DAC buffer read pointer is equal to C2[DACBFUP].
#1
DACBFRPTF
DAC Buffer Read Pointer Top Position Flag
1
1
read-write
0
The DAC buffer read pointer is not zero.
#0
1
The DAC buffer read pointer is zero.
#1
DMA
DMA Controller
DMA
0x0
0x100
0x40
registers
n
DMA0
0
DMA1
1
DMA2
2
DMA3
3
DAR0
Destination Address Register
0x104
32
read-write
n
0x0
0x0
DAR
DAR
0
32
read-write
DAR1
Destination Address Register
0x114
32
read-write
n
0x0
0x0
DAR
DAR
0
32
read-write
DAR2
Destination Address Register
0x124
32
read-write
n
0x0
0x0
DAR
DAR
0
32
read-write
DAR3
Destination Address Register
0x134
32
read-write
n
0x0
0x0
DAR
DAR
0
32
read-write
DCR0
DMA Control Register
0x10C
32
read-write
n
0x0
0x0
AA
Auto-align
28
1
read-write
0
Auto-align disabled
#0
1
If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
#1
CS
Cycle Steal
29
1
read-write
0
DMA continuously makes read/write transfers until the BCR decrements to 0.
#0
1
Forces a single read/write transfer per request.
#1
DINC
Destination Increment
19
1
read-write
0
No change to the DAR after a successful transfer.
#0
1
The DAR increments by 1, 2, 4 depending upon the size of the transfer.
#1
DMOD
Destination Address Modulo
8
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes
#0001
0010
Circular buffer size is 32 bytes
#0010
0011
Circular buffer size is 64 bytes
#0011
0100
Circular buffer size is 128 bytes
#0100
0101
Circular buffer size is 256 bytes
#0101
0110
Circular buffer size is 512 bytes
#0110
0111
Circular buffer size is 1 KB
#0111
1000
Circular buffer size is 2 KB
#1000
1001
Circular buffer size is 4 KB
#1001
1010
Circular buffer size is 8 KB
#1010
1011
Circular buffer size is 16 KB
#1011
1100
Circular buffer size is 32 KB
#1100
1101
Circular buffer size is 64 KB
#1101
1110
Circular buffer size is 128 KB
#1110
1111
Circular buffer size is 256 KB
#1111
DSIZE
Destination Size
17
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
D_REQ
Disable Request
7
1
read-write
0
ERQ bit is not affected.
#0
1
ERQ bit is cleared when the BCR is exhausted.
#1
EADREQ
Enable asynchronous DMA requests
23
1
read-write
0
Disabled
#0
1
Enabled
#1
EINT
Enable Interrupt on Completion of Transfer
31
1
read-write
0
No interrupt is generated.
#0
1
Interrupt signal is enabled.
#1
ERQ
Enable Peripheral Request
30
1
read-write
0
Peripheral request is ignored.
#0
1
Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.
#1
LCH1
Link Channel 1
2
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LCH2
Link Channel 2
0
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LINKCC
Link Channel Control
4
2
read-write
00
No channel-to-channel linking
#00
01
Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.
#01
10
Perform a link to channel LCH1 after each cycle-steal transfer
#10
11
Perform a link to channel LCH1 after the BCR decrements to 0.
#11
SINC
Source Increment
22
1
read-write
0
No change to SAR after a successful transfer.
#0
1
The SAR increments by 1, 2, 4 as determined by the transfer size.
#1
SMOD
Source Address Modulo
12
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes.
#0001
0010
Circular buffer size is 32 bytes.
#0010
0011
Circular buffer size is 64 bytes.
#0011
0100
Circular buffer size is 128 bytes.
#0100
0101
Circular buffer size is 256 bytes.
#0101
0110
Circular buffer size is 512 bytes.
#0110
0111
Circular buffer size is 1 KB.
#0111
1000
Circular buffer size is 2 KB.
#1000
1001
Circular buffer size is 4 KB.
#1001
1010
Circular buffer size is 8 KB.
#1010
1011
Circular buffer size is 16 KB.
#1011
1100
Circular buffer size is 32 KB.
#1100
1101
Circular buffer size is 64 KB.
#1101
1110
Circular buffer size is 128 KB.
#1110
1111
Circular buffer size is 256 KB.
#1111
SSIZE
Source Size
20
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
START
Start Transfer
16
1
read-write
0
DMA inactive
#0
1
The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
#1
DCR1
DMA Control Register
0x11C
32
read-write
n
0x0
0x0
AA
Auto-align
28
1
read-write
0
Auto-align disabled
#0
1
If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
#1
CS
Cycle Steal
29
1
read-write
0
DMA continuously makes read/write transfers until the BCR decrements to 0.
#0
1
Forces a single read/write transfer per request.
#1
DINC
Destination Increment
19
1
read-write
0
No change to the DAR after a successful transfer.
#0
1
The DAR increments by 1, 2, 4 depending upon the size of the transfer.
#1
DMOD
Destination Address Modulo
8
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes
#0001
0010
Circular buffer size is 32 bytes
#0010
0011
Circular buffer size is 64 bytes
#0011
0100
Circular buffer size is 128 bytes
#0100
0101
Circular buffer size is 256 bytes
#0101
0110
Circular buffer size is 512 bytes
#0110
0111
Circular buffer size is 1 KB
#0111
1000
Circular buffer size is 2 KB
#1000
1001
Circular buffer size is 4 KB
#1001
1010
Circular buffer size is 8 KB
#1010
1011
Circular buffer size is 16 KB
#1011
1100
Circular buffer size is 32 KB
#1100
1101
Circular buffer size is 64 KB
#1101
1110
Circular buffer size is 128 KB
#1110
1111
Circular buffer size is 256 KB
#1111
DSIZE
Destination Size
17
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
D_REQ
Disable Request
7
1
read-write
0
ERQ bit is not affected.
#0
1
ERQ bit is cleared when the BCR is exhausted.
#1
EADREQ
Enable asynchronous DMA requests
23
1
read-write
0
Disabled
#0
1
Enabled
#1
EINT
Enable Interrupt on Completion of Transfer
31
1
read-write
0
No interrupt is generated.
#0
1
Interrupt signal is enabled.
#1
ERQ
Enable Peripheral Request
30
1
read-write
0
Peripheral request is ignored.
#0
1
Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.
#1
LCH1
Link Channel 1
2
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LCH2
Link Channel 2
0
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LINKCC
Link Channel Control
4
2
read-write
00
No channel-to-channel linking
#00
01
Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.
#01
10
Perform a link to channel LCH1 after each cycle-steal transfer
#10
11
Perform a link to channel LCH1 after the BCR decrements to 0.
#11
SINC
Source Increment
22
1
read-write
0
No change to SAR after a successful transfer.
#0
1
The SAR increments by 1, 2, 4 as determined by the transfer size.
#1
SMOD
Source Address Modulo
12
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes.
#0001
0010
Circular buffer size is 32 bytes.
#0010
0011
Circular buffer size is 64 bytes.
#0011
0100
Circular buffer size is 128 bytes.
#0100
0101
Circular buffer size is 256 bytes.
#0101
0110
Circular buffer size is 512 bytes.
#0110
0111
Circular buffer size is 1 KB.
#0111
1000
Circular buffer size is 2 KB.
#1000
1001
Circular buffer size is 4 KB.
#1001
1010
Circular buffer size is 8 KB.
#1010
1011
Circular buffer size is 16 KB.
#1011
1100
Circular buffer size is 32 KB.
#1100
1101
Circular buffer size is 64 KB.
#1101
1110
Circular buffer size is 128 KB.
#1110
1111
Circular buffer size is 256 KB.
#1111
SSIZE
Source Size
20
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
START
Start Transfer
16
1
read-write
0
DMA inactive
#0
1
The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
#1
DCR2
DMA Control Register
0x12C
32
read-write
n
0x0
0x0
AA
Auto-align
28
1
read-write
0
Auto-align disabled
#0
1
If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
#1
CS
Cycle Steal
29
1
read-write
0
DMA continuously makes read/write transfers until the BCR decrements to 0.
#0
1
Forces a single read/write transfer per request.
#1
DINC
Destination Increment
19
1
read-write
0
No change to the DAR after a successful transfer.
#0
1
The DAR increments by 1, 2, 4 depending upon the size of the transfer.
#1
DMOD
Destination Address Modulo
8
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes
#0001
0010
Circular buffer size is 32 bytes
#0010
0011
Circular buffer size is 64 bytes
#0011
0100
Circular buffer size is 128 bytes
#0100
0101
Circular buffer size is 256 bytes
#0101
0110
Circular buffer size is 512 bytes
#0110
0111
Circular buffer size is 1 KB
#0111
1000
Circular buffer size is 2 KB
#1000
1001
Circular buffer size is 4 KB
#1001
1010
Circular buffer size is 8 KB
#1010
1011
Circular buffer size is 16 KB
#1011
1100
Circular buffer size is 32 KB
#1100
1101
Circular buffer size is 64 KB
#1101
1110
Circular buffer size is 128 KB
#1110
1111
Circular buffer size is 256 KB
#1111
DSIZE
Destination Size
17
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
D_REQ
Disable Request
7
1
read-write
0
ERQ bit is not affected.
#0
1
ERQ bit is cleared when the BCR is exhausted.
#1
EADREQ
Enable asynchronous DMA requests
23
1
read-write
0
Disabled
#0
1
Enabled
#1
EINT
Enable Interrupt on Completion of Transfer
31
1
read-write
0
No interrupt is generated.
#0
1
Interrupt signal is enabled.
#1
ERQ
Enable Peripheral Request
30
1
read-write
0
Peripheral request is ignored.
#0
1
Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.
#1
LCH1
Link Channel 1
2
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LCH2
Link Channel 2
0
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LINKCC
Link Channel Control
4
2
read-write
00
No channel-to-channel linking
#00
01
Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.
#01
10
Perform a link to channel LCH1 after each cycle-steal transfer
#10
11
Perform a link to channel LCH1 after the BCR decrements to 0.
#11
SINC
Source Increment
22
1
read-write
0
No change to SAR after a successful transfer.
#0
1
The SAR increments by 1, 2, 4 as determined by the transfer size.
#1
SMOD
Source Address Modulo
12
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes.
#0001
0010
Circular buffer size is 32 bytes.
#0010
0011
Circular buffer size is 64 bytes.
#0011
0100
Circular buffer size is 128 bytes.
#0100
0101
Circular buffer size is 256 bytes.
#0101
0110
Circular buffer size is 512 bytes.
#0110
0111
Circular buffer size is 1 KB.
#0111
1000
Circular buffer size is 2 KB.
#1000
1001
Circular buffer size is 4 KB.
#1001
1010
Circular buffer size is 8 KB.
#1010
1011
Circular buffer size is 16 KB.
#1011
1100
Circular buffer size is 32 KB.
#1100
1101
Circular buffer size is 64 KB.
#1101
1110
Circular buffer size is 128 KB.
#1110
1111
Circular buffer size is 256 KB.
#1111
SSIZE
Source Size
20
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
START
Start Transfer
16
1
read-write
0
DMA inactive
#0
1
The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
#1
DCR3
DMA Control Register
0x13C
32
read-write
n
0x0
0x0
AA
Auto-align
28
1
read-write
0
Auto-align disabled
#0
1
If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
#1
CS
Cycle Steal
29
1
read-write
0
DMA continuously makes read/write transfers until the BCR decrements to 0.
#0
1
Forces a single read/write transfer per request.
#1
DINC
Destination Increment
19
1
read-write
0
No change to the DAR after a successful transfer.
#0
1
The DAR increments by 1, 2, 4 depending upon the size of the transfer.
#1
DMOD
Destination Address Modulo
8
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes
#0001
0010
Circular buffer size is 32 bytes
#0010
0011
Circular buffer size is 64 bytes
#0011
0100
Circular buffer size is 128 bytes
#0100
0101
Circular buffer size is 256 bytes
#0101
0110
Circular buffer size is 512 bytes
#0110
0111
Circular buffer size is 1 KB
#0111
1000
Circular buffer size is 2 KB
#1000
1001
Circular buffer size is 4 KB
#1001
1010
Circular buffer size is 8 KB
#1010
1011
Circular buffer size is 16 KB
#1011
1100
Circular buffer size is 32 KB
#1100
1101
Circular buffer size is 64 KB
#1101
1110
Circular buffer size is 128 KB
#1110
1111
Circular buffer size is 256 KB
#1111
DSIZE
Destination Size
17
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
D_REQ
Disable Request
7
1
read-write
0
ERQ bit is not affected.
#0
1
ERQ bit is cleared when the BCR is exhausted.
#1
EADREQ
Enable asynchronous DMA requests
23
1
read-write
0
Disabled
#0
1
Enabled
#1
EINT
Enable Interrupt on Completion of Transfer
31
1
read-write
0
No interrupt is generated.
#0
1
Interrupt signal is enabled.
#1
ERQ
Enable Peripheral Request
30
1
read-write
0
Peripheral request is ignored.
#0
1
Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.
#1
LCH1
Link Channel 1
2
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LCH2
Link Channel 2
0
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LINKCC
Link Channel Control
4
2
read-write
00
No channel-to-channel linking
#00
01
Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.
#01
10
Perform a link to channel LCH1 after each cycle-steal transfer
#10
11
Perform a link to channel LCH1 after the BCR decrements to 0.
#11
SINC
Source Increment
22
1
read-write
0
No change to SAR after a successful transfer.
#0
1
The SAR increments by 1, 2, 4 as determined by the transfer size.
#1
SMOD
Source Address Modulo
12
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes.
#0001
0010
Circular buffer size is 32 bytes.
#0010
0011
Circular buffer size is 64 bytes.
#0011
0100
Circular buffer size is 128 bytes.
#0100
0101
Circular buffer size is 256 bytes.
#0101
0110
Circular buffer size is 512 bytes.
#0110
0111
Circular buffer size is 1 KB.
#0111
1000
Circular buffer size is 2 KB.
#1000
1001
Circular buffer size is 4 KB.
#1001
1010
Circular buffer size is 8 KB.
#1010
1011
Circular buffer size is 16 KB.
#1011
1100
Circular buffer size is 32 KB.
#1100
1101
Circular buffer size is 64 KB.
#1101
1110
Circular buffer size is 128 KB.
#1110
1111
Circular buffer size is 256 KB.
#1111
SSIZE
Source Size
20
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
START
Start Transfer
16
1
read-write
0
DMA inactive
#0
1
The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
#1
DSR0
DMA_DSR0 register.
0x10B
8
read-write
n
0x0
0x0
DSR1
DMA_DSR1 register.
0x11B
8
read-write
n
0x0
0x0
DSR2
DMA_DSR2 register.
0x12B
8
read-write
n
0x0
0x0
DSR3
DMA_DSR3 register.
0x13B
8
read-write
n
0x0
0x0
DSR_BCR0
DMA Status Register / Byte Count Register
0x108
32
read-write
n
0x0
0x0
BCR
BCR
0
24
read-write
BED
Bus Error on Destination
28
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the write portion of a transfer.
#1
BES
Bus Error on Source
29
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the read portion of a transfer.
#1
BSY
Busy
25
1
read-only
0
DMA channel is inactive. Cleared when the DMA has finished the last transaction.
#0
1
BSY is set the first time the channel is enabled after a transfer is initiated.
#1
CE
Configuration Error
30
1
read-only
0
No configuration error exists.
#0
1
A configuration error has occurred.
#1
DONE
Transactions Done
24
1
read-write
0
DMA transfer is not yet complete. Writing a 0 has no effect.
#0
1
DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
#1
REQ
Request
26
1
read-only
0
No request is pending or the channel is currently active. Cleared when the channel is selected.
#0
1
The DMA channel has a transfer remaining and the channel is not selected.
#1
DSR_BCR1
DMA Status Register / Byte Count Register
0x118
32
read-write
n
0x0
0x0
BCR
BCR
0
24
read-write
BED
Bus Error on Destination
28
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the write portion of a transfer.
#1
BES
Bus Error on Source
29
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the read portion of a transfer.
#1
BSY
Busy
25
1
read-only
0
DMA channel is inactive. Cleared when the DMA has finished the last transaction.
#0
1
BSY is set the first time the channel is enabled after a transfer is initiated.
#1
CE
Configuration Error
30
1
read-only
0
No configuration error exists.
#0
1
A configuration error has occurred.
#1
DONE
Transactions Done
24
1
read-write
0
DMA transfer is not yet complete. Writing a 0 has no effect.
#0
1
DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
#1
REQ
Request
26
1
read-only
0
No request is pending or the channel is currently active. Cleared when the channel is selected.
#0
1
The DMA channel has a transfer remaining and the channel is not selected.
#1
DSR_BCR2
DMA Status Register / Byte Count Register
0x128
32
read-write
n
0x0
0x0
BCR
BCR
0
24
read-write
BED
Bus Error on Destination
28
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the write portion of a transfer.
#1
BES
Bus Error on Source
29
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the read portion of a transfer.
#1
BSY
Busy
25
1
read-only
0
DMA channel is inactive. Cleared when the DMA has finished the last transaction.
#0
1
BSY is set the first time the channel is enabled after a transfer is initiated.
#1
CE
Configuration Error
30
1
read-only
0
No configuration error exists.
#0
1
A configuration error has occurred.
#1
DONE
Transactions Done
24
1
read-write
0
DMA transfer is not yet complete. Writing a 0 has no effect.
#0
1
DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
#1
REQ
Request
26
1
read-only
0
No request is pending or the channel is currently active. Cleared when the channel is selected.
#0
1
The DMA channel has a transfer remaining and the channel is not selected.
#1
DSR_BCR3
DMA Status Register / Byte Count Register
0x138
32
read-write
n
0x0
0x0
BCR
BCR
0
24
read-write
BED
Bus Error on Destination
28
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the write portion of a transfer.
#1
BES
Bus Error on Source
29
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the read portion of a transfer.
#1
BSY
Busy
25
1
read-only
0
DMA channel is inactive. Cleared when the DMA has finished the last transaction.
#0
1
BSY is set the first time the channel is enabled after a transfer is initiated.
#1
CE
Configuration Error
30
1
read-only
0
No configuration error exists.
#0
1
A configuration error has occurred.
#1
DONE
Transactions Done
24
1
read-write
0
DMA transfer is not yet complete. Writing a 0 has no effect.
#0
1
DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
#1
REQ
Request
26
1
read-only
0
No request is pending or the channel is currently active. Cleared when the channel is selected.
#0
1
The DMA channel has a transfer remaining and the channel is not selected.
#1
SAR0
Source Address Register
0x100
32
read-write
n
0x0
0x0
SAR
SAR
0
32
read-write
SAR1
Source Address Register
0x110
32
read-write
n
0x0
0x0
SAR
SAR
0
32
read-write
SAR2
Source Address Register
0x120
32
read-write
n
0x0
0x0
SAR
SAR
0
32
read-write
SAR3
Source Address Register
0x130
32
read-write
n
0x0
0x0
SAR
SAR
0
32
read-write
DMAMUX0
DMA channel multiplexor
DMAMUX0
0x0
0x0
0x4
registers
n
CHCFG0
Channel Configuration register
0x0
8
read-write
n
0x0
0x0
ENBL
DMA Channel Enable
7
1
read-write
0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#0
1
DMA channel is enabled
#1
SOURCE
DMA Channel Source (Slot)
0
6
read-write
000000
Disable_Signal
#0
000010
LPUART0_Rx_Signal
#10
000100
LPUART1_Rx_Signal
#100
010000
SPI0_Rx_Signal
#10000
100000
TPM1_Channel0_Signal
#100000
100001
TPM1_Channel1_Signal
#100001
010001
SPI0_Tx_Signal
#10001
100010
TPM2_Channel0_Signal
#100010
100011
TPM2_Channel1_Signal
#100011
010010
SPI1_Rx_Signal
#10010
010011
SPI1_Tx_Signal
#10011
000101
LPUART1_Tx_Signal
#101
001010
FlexIO_Channel0_Signal
#1010
101000
ADC0_Signal
#101000
101010
CMP0_Signal
#101010
001011
FlexIO_Channel1_Signal
#1011
010110
I2C0_Signal
#10110
101101
DAC0_Signal
#101101
010111
I2C1_Signal
#10111
000011
LPUART0_Tx_Signal
#11
000110
UART2_Rx_Signal
#110
001100
FlexIO_Channel2_Signal
#1100
011000
TPM0_Channel0_Signal
#11000
110001
Port_A_Signal
#110001
011001
TPM0_Channel1_Signal
#11001
110011
Port_C_Signal
#110011
001101
FlexIO_Channel3_Signal
#1101
011010
TPM0_Channel2_Signal
#11010
110100
Port_D_Signal
#110100
011011
TPM0_Channel3_Signal
#11011
110110
TPM0_Overflow_Signal
#110110
110111
TPM1_Overflow_Signal
#110111
000111
UART2_Tx_Signal
#111
011100
TPM0_Channel4_Signal
#11100
111000
TPM2_Overflow_Signal
#111000
011101
TPM0_Channel5_Signal
#11101
111100
AlwaysOn60_Signal
#111100
111101
AlwaysOn61_Signal
#111101
111110
AlwaysOn62_Signal
#111110
111111
AlwaysOn63_Signal
#111111
TRIG
DMA Channel Trigger Enable
6
1
read-write
0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#0
1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
#1
CHCFG1
Channel Configuration register
0x1
8
read-write
n
0x0
0x0
ENBL
DMA Channel Enable
7
1
read-write
0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#0
1
DMA channel is enabled
#1
SOURCE
DMA Channel Source (Slot)
0
6
read-write
000000
Disable_Signal
#0
000010
LPUART0_Rx_Signal
#10
000100
LPUART1_Rx_Signal
#100
010000
SPI0_Rx_Signal
#10000
100000
TPM1_Channel0_Signal
#100000
100001
TPM1_Channel1_Signal
#100001
010001
SPI0_Tx_Signal
#10001
100010
TPM2_Channel0_Signal
#100010
100011
TPM2_Channel1_Signal
#100011
010010
SPI1_Rx_Signal
#10010
010011
SPI1_Tx_Signal
#10011
000101
LPUART1_Tx_Signal
#101
001010
FlexIO_Channel0_Signal
#1010
101000
ADC0_Signal
#101000
101010
CMP0_Signal
#101010
001011
FlexIO_Channel1_Signal
#1011
010110
I2C0_Signal
#10110
101101
DAC0_Signal
#101101
010111
I2C1_Signal
#10111
000011
LPUART0_Tx_Signal
#11
000110
UART2_Rx_Signal
#110
001100
FlexIO_Channel2_Signal
#1100
011000
TPM0_Channel0_Signal
#11000
110001
Port_A_Signal
#110001
011001
TPM0_Channel1_Signal
#11001
110011
Port_C_Signal
#110011
001101
FlexIO_Channel3_Signal
#1101
011010
TPM0_Channel2_Signal
#11010
110100
Port_D_Signal
#110100
011011
TPM0_Channel3_Signal
#11011
110110
TPM0_Overflow_Signal
#110110
110111
TPM1_Overflow_Signal
#110111
000111
UART2_Tx_Signal
#111
011100
TPM0_Channel4_Signal
#11100
111000
TPM2_Overflow_Signal
#111000
011101
TPM0_Channel5_Signal
#11101
111100
AlwaysOn60_Signal
#111100
111101
AlwaysOn61_Signal
#111101
111110
AlwaysOn62_Signal
#111110
111111
AlwaysOn63_Signal
#111111
TRIG
DMA Channel Trigger Enable
6
1
read-write
0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#0
1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
#1
CHCFG2
Channel Configuration register
0x3
8
read-write
n
0x0
0x0
ENBL
DMA Channel Enable
7
1
read-write
0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#0
1
DMA channel is enabled
#1
SOURCE
DMA Channel Source (Slot)
0
6
read-write
000000
Disable_Signal
#0
000010
LPUART0_Rx_Signal
#10
000100
LPUART1_Rx_Signal
#100
010000
SPI0_Rx_Signal
#10000
100000
TPM1_Channel0_Signal
#100000
100001
TPM1_Channel1_Signal
#100001
010001
SPI0_Tx_Signal
#10001
100010
TPM2_Channel0_Signal
#100010
100011
TPM2_Channel1_Signal
#100011
010010
SPI1_Rx_Signal
#10010
010011
SPI1_Tx_Signal
#10011
000101
LPUART1_Tx_Signal
#101
001010
FlexIO_Channel0_Signal
#1010
101000
ADC0_Signal
#101000
101010
CMP0_Signal
#101010
001011
FlexIO_Channel1_Signal
#1011
010110
I2C0_Signal
#10110
101101
DAC0_Signal
#101101
010111
I2C1_Signal
#10111
000011
LPUART0_Tx_Signal
#11
000110
UART2_Rx_Signal
#110
001100
FlexIO_Channel2_Signal
#1100
011000
TPM0_Channel0_Signal
#11000
110001
Port_A_Signal
#110001
011001
TPM0_Channel1_Signal
#11001
110011
Port_C_Signal
#110011
001101
FlexIO_Channel3_Signal
#1101
011010
TPM0_Channel2_Signal
#11010
110100
Port_D_Signal
#110100
011011
TPM0_Channel3_Signal
#11011
110110
TPM0_Overflow_Signal
#110110
110111
TPM1_Overflow_Signal
#110111
000111
UART2_Tx_Signal
#111
011100
TPM0_Channel4_Signal
#11100
111000
TPM2_Overflow_Signal
#111000
011101
TPM0_Channel5_Signal
#11101
111100
AlwaysOn60_Signal
#111100
111101
AlwaysOn61_Signal
#111101
111110
AlwaysOn62_Signal
#111110
111111
AlwaysOn63_Signal
#111111
TRIG
DMA Channel Trigger Enable
6
1
read-write
0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#0
1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
#1
CHCFG3
Channel Configuration register
0x6
8
read-write
n
0x0
0x0
ENBL
DMA Channel Enable
7
1
read-write
0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#0
1
DMA channel is enabled
#1
SOURCE
DMA Channel Source (Slot)
0
6
read-write
000000
Disable_Signal
#0
000010
LPUART0_Rx_Signal
#10
000100
LPUART1_Rx_Signal
#100
010000
SPI0_Rx_Signal
#10000
100000
TPM1_Channel0_Signal
#100000
100001
TPM1_Channel1_Signal
#100001
010001
SPI0_Tx_Signal
#10001
100010
TPM2_Channel0_Signal
#100010
100011
TPM2_Channel1_Signal
#100011
010010
SPI1_Rx_Signal
#10010
010011
SPI1_Tx_Signal
#10011
000101
LPUART1_Tx_Signal
#101
001010
FlexIO_Channel0_Signal
#1010
101000
ADC0_Signal
#101000
101010
CMP0_Signal
#101010
001011
FlexIO_Channel1_Signal
#1011
010110
I2C0_Signal
#10110
101101
DAC0_Signal
#101101
010111
I2C1_Signal
#10111
000011
LPUART0_Tx_Signal
#11
000110
UART2_Rx_Signal
#110
001100
FlexIO_Channel2_Signal
#1100
011000
TPM0_Channel0_Signal
#11000
110001
Port_A_Signal
#110001
011001
TPM0_Channel1_Signal
#11001
110011
Port_C_Signal
#110011
001101
FlexIO_Channel3_Signal
#1101
011010
TPM0_Channel2_Signal
#11010
110100
Port_D_Signal
#110100
011011
TPM0_Channel3_Signal
#11011
110110
TPM0_Overflow_Signal
#110110
110111
TPM1_Overflow_Signal
#110111
000111
UART2_Tx_Signal
#111
011100
TPM0_Channel4_Signal
#11100
111000
TPM2_Overflow_Signal
#111000
011101
TPM0_Channel5_Signal
#11101
111100
AlwaysOn60_Signal
#111100
111101
AlwaysOn61_Signal
#111101
111110
AlwaysOn62_Signal
#111110
111111
AlwaysOn63_Signal
#111111
TRIG
DMA Channel Trigger Enable
6
1
read-write
0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#0
1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
#1
FGPIOA
General Purpose Input/Output
FGPIO
0x0
0x0
0x18
registers
n
PCOR
Port Clear Output Register
0x8
32
read-write
n
0x0
0x0
PTCO
Port Clear Output
0
32
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
read-write
n
0x0
0x0
PTSO
Port Set Output
0
32
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
read-write
n
0x0
0x0
PTTO
Port Toggle Output
0
32
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
FGPIOB
General Purpose Input/Output
FGPIO
0x0
0x0
0x18
registers
n
PCOR
Port Clear Output Register
0x8
32
read-write
n
0x0
0x0
PTCO
Port Clear Output
0
32
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
read-write
n
0x0
0x0
PTSO
Port Set Output
0
32
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
read-write
n
0x0
0x0
PTTO
Port Toggle Output
0
32
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
FGPIOC
General Purpose Input/Output
FGPIO
0x0
0x0
0x18
registers
n
PCOR
Port Clear Output Register
0x8
32
read-write
n
0x0
0x0
PTCO
Port Clear Output
0
32
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
read-write
n
0x0
0x0
PTSO
Port Set Output
0
32
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
read-write
n
0x0
0x0
PTTO
Port Toggle Output
0
32
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
FGPIOD
General Purpose Input/Output
FGPIO
0x0
0x0
0x18
registers
n
PCOR
Port Clear Output Register
0x8
32
read-write
n
0x0
0x0
PTCO
Port Clear Output
0
32
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
read-write
n
0x0
0x0
PTSO
Port Set Output
0
32
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
read-write
n
0x0
0x0
PTTO
Port Toggle Output
0
32
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
FGPIOE
General Purpose Input/Output
FGPIO
0x0
0x0
0x18
registers
n
PCOR
Port Clear Output Register
0x8
32
read-write
n
0x0
0x0
PTCO
Port Clear Output
0
32
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
read-write
n
0x0
0x0
PTSO
Port Set Output
0
32
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
read-write
n
0x0
0x0
PTTO
Port Toggle Output
0
32
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
FLEXIO
The FLEXIO Memory Map/Register Definition can be found here.
FLEXIO
0x0
0x0
0x510
registers
n
UART2_FLEXIO
14
CTRL
FlexIO Control Register
0x8
32
read-write
n
0x0
0x0
DBGE
Debug Enable
30
1
read-write
0
FlexIO is disabled in debug modes.
#0
1
FlexIO is enabled in debug modes
#1
DOZEN
Doze Enable
31
1
read-write
0
FlexIO enabled in Doze modes.
#0
1
FlexIO disabled in Doze modes.
#1
FASTACC
Fast Access
2
1
read-write
0
Configures for normal register accesses to FlexIO
#0
1
Configures for fast register accesses to FlexIO
#1
FLEXEN
FlexIO Enable
0
1
read-write
0
FlexIO module is disabled.
#0
1
FlexIO module is enabled.
#1
SWRST
Software Reset
1
1
read-write
0
Software reset is disabled
#0
1
Software reset is enabled, all FlexIO registers except the Control Register are reset.
#1
PARAM
Parameter Register
0x4
32
read-only
n
0x0
0x0
PIN
Pin Number
16
8
read-only
SHIFTER
Shifter Number
0
8
read-only
TIMER
Timer Number
8
8
read-only
TRIGGER
Trigger Number
24
8
read-only
SHIFTBUF0
Shifter Buffer N Register
0x400
32
read-write
n
0x0
0x0
SHIFTBUF
Shift Buffer
0
32
read-write
SHIFTBUF1
Shifter Buffer N Register
0x604
32
read-write
n
0x0
0x0
SHIFTBUF
Shift Buffer
0
32
read-write
SHIFTBUF2
Shifter Buffer N Register
0x80C
32
read-write
n
0x0
0x0
SHIFTBUF
Shift Buffer
0
32
read-write
SHIFTBUF3
Shifter Buffer N Register
0xA18
32
read-write
n
0x0
0x0
SHIFTBUF
Shift Buffer
0
32
read-write
SHIFTBUFBBS0
Shifter Buffer N Bit Byte Swapped Register
0x700
32
read-write
n
0x0
0x0
SHIFTBUFBBS
Shift Buffer
0
32
read-write
SHIFTBUFBBS1
Shifter Buffer N Bit Byte Swapped Register
0xA84
32
read-write
n
0x0
0x0
SHIFTBUFBBS
Shift Buffer
0
32
read-write
SHIFTBUFBBS2
Shifter Buffer N Bit Byte Swapped Register
0xE0C
32
read-write
n
0x0
0x0
SHIFTBUFBBS
Shift Buffer
0
32
read-write
SHIFTBUFBBS3
Shifter Buffer N Bit Byte Swapped Register
0x1198
32
read-write
n
0x0
0x0
SHIFTBUFBBS
Shift Buffer
0
32
read-write
SHIFTBUFBIS0
Shifter Buffer N Bit Swapped Register
0x500
32
read-write
n
0x0
0x0
SHIFTBUFBIS
Shift Buffer
0
32
read-write
SHIFTBUFBIS1
Shifter Buffer N Bit Swapped Register
0x784
32
read-write
n
0x0
0x0
SHIFTBUFBIS
Shift Buffer
0
32
read-write
SHIFTBUFBIS2
Shifter Buffer N Bit Swapped Register
0xA0C
32
read-write
n
0x0
0x0
SHIFTBUFBIS
Shift Buffer
0
32
read-write
SHIFTBUFBIS3
Shifter Buffer N Bit Swapped Register
0xC98
32
read-write
n
0x0
0x0
SHIFTBUFBIS
Shift Buffer
0
32
read-write
SHIFTBUFBYS0
Shifter Buffer N Byte Swapped Register
0x600
32
read-write
n
0x0
0x0
SHIFTBUFBYS
Shift Buffer
0
32
read-write
SHIFTBUFBYS1
Shifter Buffer N Byte Swapped Register
0x904
32
read-write
n
0x0
0x0
SHIFTBUFBYS
Shift Buffer
0
32
read-write
SHIFTBUFBYS2
Shifter Buffer N Byte Swapped Register
0xC0C
32
read-write
n
0x0
0x0
SHIFTBUFBYS
Shift Buffer
0
32
read-write
SHIFTBUFBYS3
Shifter Buffer N Byte Swapped Register
0xF18
32
read-write
n
0x0
0x0
SHIFTBUFBYS
Shift Buffer
0
32
read-write
SHIFTCFG0
Shifter Configuration N Register
0x200
32
read-write
n
0x0
0x0
INSRC
Input Source
8
1
read-write
0
Pin
#0
1
Shifter N+1 Output
#1
SSTART
Shifter Start bit
0
2
read-write
00
Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
#00
01
Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
#01
10
Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
#10
11
Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
#11
SSTOP
Shifter Stop bit
4
2
read-write
00
Stop bit disabled for transmitter/receiver/match store
#00
01
Reserved for transmitter/receiver/match store
#01
10
Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
#10
11
Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
#11
SHIFTCFG1
Shifter Configuration N Register
0x304
32
read-write
n
0x0
0x0
INSRC
Input Source
8
1
read-write
0
Pin
#0
1
Shifter N+1 Output
#1
SSTART
Shifter Start bit
0
2
read-write
00
Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
#00
01
Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
#01
10
Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
#10
11
Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
#11
SSTOP
Shifter Stop bit
4
2
read-write
00
Stop bit disabled for transmitter/receiver/match store
#00
01
Reserved for transmitter/receiver/match store
#01
10
Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
#10
11
Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
#11
SHIFTCFG2
Shifter Configuration N Register
0x40C
32
read-write
n
0x0
0x0
INSRC
Input Source
8
1
read-write
0
Pin
#0
1
Shifter N+1 Output
#1
SSTART
Shifter Start bit
0
2
read-write
00
Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
#00
01
Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
#01
10
Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
#10
11
Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
#11
SSTOP
Shifter Stop bit
4
2
read-write
00
Stop bit disabled for transmitter/receiver/match store
#00
01
Reserved for transmitter/receiver/match store
#01
10
Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
#10
11
Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
#11
SHIFTCFG3
Shifter Configuration N Register
0x518
32
read-write
n
0x0
0x0
INSRC
Input Source
8
1
read-write
0
Pin
#0
1
Shifter N+1 Output
#1
SSTART
Shifter Start bit
0
2
read-write
00
Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
#00
01
Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
#01
10
Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
#10
11
Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
#11
SSTOP
Shifter Stop bit
4
2
read-write
00
Stop bit disabled for transmitter/receiver/match store
#00
01
Reserved for transmitter/receiver/match store
#01
10
Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
#10
11
Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
#11
SHIFTCTL0
Shifter Control N Register
0x100
32
read-write
n
0x0
0x0
PINCFG
Shifter Pin Configuration
16
2
read-write
00
Shifter pin output disabled
#00
01
Shifter pin open drain or bidirectional output enable
#01
10
Shifter pin bidirectional output data
#10
11
Shifter pin output
#11
PINPOL
Shifter Pin Polarity
7
1
read-write
0
Pin is active high
#0
1
Pin is active low
#1
PINSEL
Shifter Pin Select
8
3
read-write
SMOD
Shifter Mode
0
3
read-write
000
Disabled.
#000
001
Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
#001
010
Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
#010
100
Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
#100
101
Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
#101
TIMPOL
Timer Polarity
23
1
read-write
0
Shift on posedge of Shift clock
#0
1
Shift on negedge of Shift clock
#1
TIMSEL
Timer Select
24
2
read-write
SHIFTCTL1
Shifter Control N Register
0x184
32
read-write
n
0x0
0x0
PINCFG
Shifter Pin Configuration
16
2
read-write
00
Shifter pin output disabled
#00
01
Shifter pin open drain or bidirectional output enable
#01
10
Shifter pin bidirectional output data
#10
11
Shifter pin output
#11
PINPOL
Shifter Pin Polarity
7
1
read-write
0
Pin is active high
#0
1
Pin is active low
#1
PINSEL
Shifter Pin Select
8
3
read-write
SMOD
Shifter Mode
0
3
read-write
000
Disabled.
#000
001
Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
#001
010
Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
#010
100
Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
#100
101
Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
#101
TIMPOL
Timer Polarity
23
1
read-write
0
Shift on posedge of Shift clock
#0
1
Shift on negedge of Shift clock
#1
TIMSEL
Timer Select
24
2
read-write
SHIFTCTL2
Shifter Control N Register
0x20C
32
read-write
n
0x0
0x0
PINCFG
Shifter Pin Configuration
16
2
read-write
00
Shifter pin output disabled
#00
01
Shifter pin open drain or bidirectional output enable
#01
10
Shifter pin bidirectional output data
#10
11
Shifter pin output
#11
PINPOL
Shifter Pin Polarity
7
1
read-write
0
Pin is active high
#0
1
Pin is active low
#1
PINSEL
Shifter Pin Select
8
3
read-write
SMOD
Shifter Mode
0
3
read-write
000
Disabled.
#000
001
Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
#001
010
Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
#010
100
Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
#100
101
Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
#101
TIMPOL
Timer Polarity
23
1
read-write
0
Shift on posedge of Shift clock
#0
1
Shift on negedge of Shift clock
#1
TIMSEL
Timer Select
24
2
read-write
SHIFTCTL3
Shifter Control N Register
0x298
32
read-write
n
0x0
0x0
PINCFG
Shifter Pin Configuration
16
2
read-write
00
Shifter pin output disabled
#00
01
Shifter pin open drain or bidirectional output enable
#01
10
Shifter pin bidirectional output data
#10
11
Shifter pin output
#11
PINPOL
Shifter Pin Polarity
7
1
read-write
0
Pin is active high
#0
1
Pin is active low
#1
PINSEL
Shifter Pin Select
8
3
read-write
SMOD
Shifter Mode
0
3
read-write
000
Disabled.
#000
001
Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
#001
010
Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
#010
100
Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
#100
101
Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
#101
TIMPOL
Timer Polarity
23
1
read-write
0
Shift on posedge of Shift clock
#0
1
Shift on negedge of Shift clock
#1
TIMSEL
Timer Select
24
2
read-write
SHIFTEIEN
Shifter Error Interrupt Enable
0x24
32
read-write
n
0x0
0x0
SEIE
Shifter Error Interrupt Enable
0
4
read-write
0
Shifter Error Flag interrupt disabled
#0000
1
Shifter Error Flag interrupt enabled
#0001
SHIFTERR
Shifter Error Register
0x14
32
read-write
n
0x0
0x0
SEF
Shifter Error Flags
0
4
read-write
0
Shifter Error Flag is clear
#0000
1
Shifter Error Flag is set
#0001
SHIFTSDEN
Shifter Status DMA Enable
0x30
32
read-write
n
0x0
0x0
SSDE
Shifter Status DMA Enable
0
4
read-write
0
Shifter Status Flag DMA request is disabled
#0000
1
Shifter Status Flag DMA request is enabled
#0001
SHIFTSIEN
Shifter Status Interrupt Enable
0x20
32
read-write
n
0x0
0x0
SSIE
Shifter Status Interrupt Enable
0
4
read-write
0
Shifter Status Flag interrupt disabled
#0000
1
Shifter Status Flag interrupt enabled
#0001
SHIFTSTAT
Shifter Status Register
0x10
32
read-write
n
0x0
0x0
SSF
Shifter Status Flag
0
4
read-write
0
Status flag is clear
#0000
1
Status flag is set
#0001
TIMCFG0
Timer Configuration N Register
0x900
32
read-write
n
0x0
0x0
TIMDEC
Timer Decrement
20
2
read-write
00
Decrement counter on FlexIO clock, Shift clock equals Timer output.
#00
01
Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
#01
10
Decrement counter on Pin input (both edges), Shift clock equals Pin input.
#10
11
Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
#11
TIMDIS
Timer Disable
12
3
read-write
000
Timer never disabled
#000
001
Timer disabled on Timer N-1 disable
#001
010
Timer disabled on Timer compare
#010
011
Timer disabled on Timer compare and Trigger Low
#011
100
Timer disabled on Pin rising or falling edge
#100
101
Timer disabled on Pin rising or falling edge provided Trigger is high
#101
110
Timer disabled on Trigger falling edge
#110
TIMENA
Timer Enable
8
3
read-write
000
Timer always enabled
#000
001
Timer enabled on Timer N-1 enable
#001
010
Timer enabled on Trigger high
#010
011
Timer enabled on Trigger high and Pin high
#011
100
Timer enabled on Pin rising edge
#100
101
Timer enabled on Pin rising edge and Trigger high
#101
110
Timer enabled on Trigger rising edge
#110
111
Timer enabled on Trigger rising or falling edge
#111
TIMOUT
Timer Output
24
2
read-write
00
Timer output is logic one when enabled and is not affected by timer reset
#00
01
Timer output is logic zero when enabled and is not affected by timer reset
#01
10
Timer output is logic one when enabled and on timer reset
#10
11
Timer output is logic zero when enabled and on timer reset
#11
TIMRST
Timer Reset
16
3
read-write
000
Timer never reset
#000
010
Timer reset on Timer Pin equal to Timer Output
#010
011
Timer reset on Timer Trigger equal to Timer Output
#011
100
Timer reset on Timer Pin rising edge
#100
110
Timer reset on Trigger rising edge
#110
111
Timer reset on Trigger rising or falling edge
#111
TSTART
Timer Start Bit
1
1
read-write
0
Start bit disabled
#0
1
Start bit enabled
#1
TSTOP
Timer Stop Bit
4
2
read-write
00
Stop bit disabled
#00
01
Stop bit is enabled on timer compare
#01
10
Stop bit is enabled on timer disable
#10
11
Stop bit is enabled on timer compare and timer disable
#11
TIMCFG1
Timer Configuration N Register
0xD84
32
read-write
n
0x0
0x0
TIMDEC
Timer Decrement
20
2
read-write
00
Decrement counter on FlexIO clock, Shift clock equals Timer output.
#00
01
Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
#01
10
Decrement counter on Pin input (both edges), Shift clock equals Pin input.
#10
11
Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
#11
TIMDIS
Timer Disable
12
3
read-write
000
Timer never disabled
#000
001
Timer disabled on Timer N-1 disable
#001
010
Timer disabled on Timer compare
#010
011
Timer disabled on Timer compare and Trigger Low
#011
100
Timer disabled on Pin rising or falling edge
#100
101
Timer disabled on Pin rising or falling edge provided Trigger is high
#101
110
Timer disabled on Trigger falling edge
#110
TIMENA
Timer Enable
8
3
read-write
000
Timer always enabled
#000
001
Timer enabled on Timer N-1 enable
#001
010
Timer enabled on Trigger high
#010
011
Timer enabled on Trigger high and Pin high
#011
100
Timer enabled on Pin rising edge
#100
101
Timer enabled on Pin rising edge and Trigger high
#101
110
Timer enabled on Trigger rising edge
#110
111
Timer enabled on Trigger rising or falling edge
#111
TIMOUT
Timer Output
24
2
read-write
00
Timer output is logic one when enabled and is not affected by timer reset
#00
01
Timer output is logic zero when enabled and is not affected by timer reset
#01
10
Timer output is logic one when enabled and on timer reset
#10
11
Timer output is logic zero when enabled and on timer reset
#11
TIMRST
Timer Reset
16
3
read-write
000
Timer never reset
#000
010
Timer reset on Timer Pin equal to Timer Output
#010
011
Timer reset on Timer Trigger equal to Timer Output
#011
100
Timer reset on Timer Pin rising edge
#100
110
Timer reset on Trigger rising edge
#110
111
Timer reset on Trigger rising or falling edge
#111
TSTART
Timer Start Bit
1
1
read-write
0
Start bit disabled
#0
1
Start bit enabled
#1
TSTOP
Timer Stop Bit
4
2
read-write
00
Stop bit disabled
#00
01
Stop bit is enabled on timer compare
#01
10
Stop bit is enabled on timer disable
#10
11
Stop bit is enabled on timer compare and timer disable
#11
TIMCFG2
Timer Configuration N Register
0x120C
32
read-write
n
0x0
0x0
TIMDEC
Timer Decrement
20
2
read-write
00
Decrement counter on FlexIO clock, Shift clock equals Timer output.
#00
01
Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
#01
10
Decrement counter on Pin input (both edges), Shift clock equals Pin input.
#10
11
Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
#11
TIMDIS
Timer Disable
12
3
read-write
000
Timer never disabled
#000
001
Timer disabled on Timer N-1 disable
#001
010
Timer disabled on Timer compare
#010
011
Timer disabled on Timer compare and Trigger Low
#011
100
Timer disabled on Pin rising or falling edge
#100
101
Timer disabled on Pin rising or falling edge provided Trigger is high
#101
110
Timer disabled on Trigger falling edge
#110
TIMENA
Timer Enable
8
3
read-write
000
Timer always enabled
#000
001
Timer enabled on Timer N-1 enable
#001
010
Timer enabled on Trigger high
#010
011
Timer enabled on Trigger high and Pin high
#011
100
Timer enabled on Pin rising edge
#100
101
Timer enabled on Pin rising edge and Trigger high
#101
110
Timer enabled on Trigger rising edge
#110
111
Timer enabled on Trigger rising or falling edge
#111
TIMOUT
Timer Output
24
2
read-write
00
Timer output is logic one when enabled and is not affected by timer reset
#00
01
Timer output is logic zero when enabled and is not affected by timer reset
#01
10
Timer output is logic one when enabled and on timer reset
#10
11
Timer output is logic zero when enabled and on timer reset
#11
TIMRST
Timer Reset
16
3
read-write
000
Timer never reset
#000
010
Timer reset on Timer Pin equal to Timer Output
#010
011
Timer reset on Timer Trigger equal to Timer Output
#011
100
Timer reset on Timer Pin rising edge
#100
110
Timer reset on Trigger rising edge
#110
111
Timer reset on Trigger rising or falling edge
#111
TSTART
Timer Start Bit
1
1
read-write
0
Start bit disabled
#0
1
Start bit enabled
#1
TSTOP
Timer Stop Bit
4
2
read-write
00
Stop bit disabled
#00
01
Stop bit is enabled on timer compare
#01
10
Stop bit is enabled on timer disable
#10
11
Stop bit is enabled on timer compare and timer disable
#11
TIMCFG3
Timer Configuration N Register
0x1698
32
read-write
n
0x0
0x0
TIMDEC
Timer Decrement
20
2
read-write
00
Decrement counter on FlexIO clock, Shift clock equals Timer output.
#00
01
Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
#01
10
Decrement counter on Pin input (both edges), Shift clock equals Pin input.
#10
11
Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
#11
TIMDIS
Timer Disable
12
3
read-write
000
Timer never disabled
#000
001
Timer disabled on Timer N-1 disable
#001
010
Timer disabled on Timer compare
#010
011
Timer disabled on Timer compare and Trigger Low
#011
100
Timer disabled on Pin rising or falling edge
#100
101
Timer disabled on Pin rising or falling edge provided Trigger is high
#101
110
Timer disabled on Trigger falling edge
#110
TIMENA
Timer Enable
8
3
read-write
000
Timer always enabled
#000
001
Timer enabled on Timer N-1 enable
#001
010
Timer enabled on Trigger high
#010
011
Timer enabled on Trigger high and Pin high
#011
100
Timer enabled on Pin rising edge
#100
101
Timer enabled on Pin rising edge and Trigger high
#101
110
Timer enabled on Trigger rising edge
#110
111
Timer enabled on Trigger rising or falling edge
#111
TIMOUT
Timer Output
24
2
read-write
00
Timer output is logic one when enabled and is not affected by timer reset
#00
01
Timer output is logic zero when enabled and is not affected by timer reset
#01
10
Timer output is logic one when enabled and on timer reset
#10
11
Timer output is logic zero when enabled and on timer reset
#11
TIMRST
Timer Reset
16
3
read-write
000
Timer never reset
#000
010
Timer reset on Timer Pin equal to Timer Output
#010
011
Timer reset on Timer Trigger equal to Timer Output
#011
100
Timer reset on Timer Pin rising edge
#100
110
Timer reset on Trigger rising edge
#110
111
Timer reset on Trigger rising or falling edge
#111
TSTART
Timer Start Bit
1
1
read-write
0
Start bit disabled
#0
1
Start bit enabled
#1
TSTOP
Timer Stop Bit
4
2
read-write
00
Stop bit disabled
#00
01
Stop bit is enabled on timer compare
#01
10
Stop bit is enabled on timer disable
#10
11
Stop bit is enabled on timer compare and timer disable
#11
TIMCMP0
Timer Compare N Register
0xA00
32
read-write
n
0x0
0x0
CMP
Timer Compare Value
0
16
read-write
TIMCMP1
Timer Compare N Register
0xF04
32
read-write
n
0x0
0x0
CMP
Timer Compare Value
0
16
read-write
TIMCMP2
Timer Compare N Register
0x140C
32
read-write
n
0x0
0x0
CMP
Timer Compare Value
0
16
read-write
TIMCMP3
Timer Compare N Register
0x1918
32
read-write
n
0x0
0x0
CMP
Timer Compare Value
0
16
read-write
TIMCTL0
Timer Control N Register
0x800
32
read-write
n
0x0
0x0
PINCFG
Timer Pin Configuration
16
2
read-write
00
Timer pin output disabled
#00
01
Timer pin open drain or bidirectional output enable
#01
10
Timer pin bidirectional output data
#10
11
Timer pin output
#11
PINPOL
Timer Pin Polarity
7
1
read-write
0
Pin is active high
#0
1
Pin is active low
#1
PINSEL
Timer Pin Select
8
3
read-write
TIMOD
Timer Mode
0
2
read-write
00
Timer Disabled.
#00
01
Dual 8-bit counters baud/bit mode.
#01
10
Dual 8-bit counters PWM mode.
#10
11
Single 16-bit counter mode.
#11
TRGPOL
Trigger Polarity
23
1
read-write
0
Trigger active high
#0
1
Trigger active low
#1
TRGSEL
Trigger Select
24
4
read-write
TRGSRC
Trigger Source
22
1
read-write
0
External trigger selected
#0
1
Internal trigger selected
#1
TIMCTL1
Timer Control N Register
0xC04
32
read-write
n
0x0
0x0
PINCFG
Timer Pin Configuration
16
2
read-write
00
Timer pin output disabled
#00
01
Timer pin open drain or bidirectional output enable
#01
10
Timer pin bidirectional output data
#10
11
Timer pin output
#11
PINPOL
Timer Pin Polarity
7
1
read-write
0
Pin is active high
#0
1
Pin is active low
#1
PINSEL
Timer Pin Select
8
3
read-write
TIMOD
Timer Mode
0
2
read-write
00
Timer Disabled.
#00
01
Dual 8-bit counters baud/bit mode.
#01
10
Dual 8-bit counters PWM mode.
#10
11
Single 16-bit counter mode.
#11
TRGPOL
Trigger Polarity
23
1
read-write
0
Trigger active high
#0
1
Trigger active low
#1
TRGSEL
Trigger Select
24
4
read-write
TRGSRC
Trigger Source
22
1
read-write
0
External trigger selected
#0
1
Internal trigger selected
#1
TIMCTL2
Timer Control N Register
0x100C
32
read-write
n
0x0
0x0
PINCFG
Timer Pin Configuration
16
2
read-write
00
Timer pin output disabled
#00
01
Timer pin open drain or bidirectional output enable
#01
10
Timer pin bidirectional output data
#10
11
Timer pin output
#11
PINPOL
Timer Pin Polarity
7
1
read-write
0
Pin is active high
#0
1
Pin is active low
#1
PINSEL
Timer Pin Select
8
3
read-write
TIMOD
Timer Mode
0
2
read-write
00
Timer Disabled.
#00
01
Dual 8-bit counters baud/bit mode.
#01
10
Dual 8-bit counters PWM mode.
#10
11
Single 16-bit counter mode.
#11
TRGPOL
Trigger Polarity
23
1
read-write
0
Trigger active high
#0
1
Trigger active low
#1
TRGSEL
Trigger Select
24
4
read-write
TRGSRC
Trigger Source
22
1
read-write
0
External trigger selected
#0
1
Internal trigger selected
#1
TIMCTL3
Timer Control N Register
0x1418
32
read-write
n
0x0
0x0
PINCFG
Timer Pin Configuration
16
2
read-write
00
Timer pin output disabled
#00
01
Timer pin open drain or bidirectional output enable
#01
10
Timer pin bidirectional output data
#10
11
Timer pin output
#11
PINPOL
Timer Pin Polarity
7
1
read-write
0
Pin is active high
#0
1
Pin is active low
#1
PINSEL
Timer Pin Select
8
3
read-write
TIMOD
Timer Mode
0
2
read-write
00
Timer Disabled.
#00
01
Dual 8-bit counters baud/bit mode.
#01
10
Dual 8-bit counters PWM mode.
#10
11
Single 16-bit counter mode.
#11
TRGPOL
Trigger Polarity
23
1
read-write
0
Trigger active high
#0
1
Trigger active low
#1
TRGSEL
Trigger Select
24
4
read-write
TRGSRC
Trigger Source
22
1
read-write
0
External trigger selected
#0
1
Internal trigger selected
#1
TIMIEN
Timer Interrupt Enable Register
0x28
32
read-write
n
0x0
0x0
TEIE
Timer Status Interrupt Enable
0
4
read-write
0
Timer Status Flag interrupt is disabled
#0000
1
Timer Status Flag interrupt is enabled
#0001
TIMSTAT
Timer Status Register
0x18
32
read-write
n
0x0
0x0
TSF
Timer Status Flags
0
4
read-write
0
Timer Status Flag is clear
#0000
1
Timer Status Flag is set
#0001
VERID
Version ID Register
0x0
32
read-only
n
0x0
0x0
FEATURE
Feature Specification Number
0
16
read-only
0
Standard features implemented.
#0
1
Supports state, logic and parallel modes.
#1
MAJOR
Major Version Number
24
8
read-only
MINOR
Minor Version Number
16
8
read-only
FTFA
Flash Memory Interface
FTFA
0x0
0x0
0x14
registers
n
FTFA
5
FCCOB0
Flash Common Command Object Registers
0x1A
8
read-write
n
0x0
0x0
CCOBn
The FCCOB register provides a command code and relevant parameters to the memory controller
0
8
read-write
FCCOB1
Flash Common Command Object Registers
0x13
8
read-write
n
0x0
0x0
CCOBn
The FCCOB register provides a command code and relevant parameters to the memory controller
0
8
read-write
FCCOB2
Flash Common Command Object Registers
0xD
8
read-write
n
0x0
0x0
CCOBn
The FCCOB register provides a command code and relevant parameters to the memory controller
0
8
read-write
FCCOB3
Flash Common Command Object Registers
0x8
8
read-write
n
0x0
0x0
CCOBn
The FCCOB register provides a command code and relevant parameters to the memory controller
0
8
read-write
FCCOB4
Flash Common Command Object Registers
0x40
8
read-write
n
0x0
0x0
CCOBn
The FCCOB register provides a command code and relevant parameters to the memory controller
0
8
read-write
FCCOB5
Flash Common Command Object Registers
0x35
8
read-write
n
0x0
0x0
CCOBn
The FCCOB register provides a command code and relevant parameters to the memory controller
0
8
read-write
FCCOB6
Flash Common Command Object Registers
0x2B
8
read-write
n
0x0
0x0
CCOBn
The FCCOB register provides a command code and relevant parameters to the memory controller
0
8
read-write
FCCOB7
Flash Common Command Object Registers
0x22
8
read-write
n
0x0
0x0
CCOBn
The FCCOB register provides a command code and relevant parameters to the memory controller
0
8
read-write
FCCOB8
Flash Common Command Object Registers
0x76
8
read-write
n
0x0
0x0
CCOBn
The FCCOB register provides a command code and relevant parameters to the memory controller
0
8
read-write
FCCOB9
Flash Common Command Object Registers
0x67
8
read-write
n
0x0
0x0
CCOBn
The FCCOB register provides a command code and relevant parameters to the memory controller
0
8
read-write
FCCOBA
Flash Common Command Object Registers
0x59
8
read-write
n
0x0
0x0
CCOBn
The FCCOB register provides a command code and relevant parameters to the memory controller
0
8
read-write
FCCOBB
Flash Common Command Object Registers
0x4C
8
read-write
n
0x0
0x0
CCOBn
The FCCOB register provides a command code and relevant parameters to the memory controller
0
8
read-write
FCNFG
Flash Configuration Register
0x1
8
read-write
n
0x0
0x0
CCIE
Command Complete Interrupt Enable
7
1
read-write
0
Command complete interrupt disabled
#0
1
Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
#1
ERSAREQ
Erase All Request
5
1
read-only
0
No request or request complete
#0
1
Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state.
#1
ERSSUSP
Erase Suspend
4
1
read-write
0
No suspend requested
#0
1
Suspend the current Erase Flash Sector command execution.
#1
RDCOLLIE
Read Collision Error Interrupt Enable
6
1
read-write
0
Read collision error interrupt disabled
#0
1
Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]).
#1
FOPT
Flash Option Register
0x3
8
read-only
n
0x0
0x0
OPT
Nonvolatile Option
0
8
read-only
FPROT0
Program Flash Protection Registers
0x56
8
read-write
n
0x0
0x0
PROT
Program Flash Region Protect
0
8
read-write
0
Program flash region is protected.
#0
1
Program flash region is not protected
#1
FPROT1
Program Flash Protection Registers
0x43
8
read-write
n
0x0
0x0
PROT
Program Flash Region Protect
0
8
read-write
0
Program flash region is protected.
#0
1
Program flash region is not protected
#1
FPROT2
Program Flash Protection Registers
0x31
8
read-write
n
0x0
0x0
PROT
Program Flash Region Protect
0
8
read-write
0
Program flash region is protected.
#0
1
Program flash region is not protected
#1
FPROT3
Program Flash Protection Registers
0x20
8
read-write
n
0x0
0x0
PROT
Program Flash Region Protect
0
8
read-write
0
Program flash region is protected.
#0
1
Program flash region is not protected
#1
FSEC
Flash Security Register
0x2
8
read-only
n
0x0
0x0
FSLACC
Factory Security Level Access Code
2
2
read-only
00
NXP factory access granted
#00
01
NXP factory access denied
#01
10
NXP factory access denied
#10
11
NXP factory access granted
#11
KEYEN
Backdoor Key Security Enable
6
2
read-only
00
Backdoor key access disabled
#00
01
Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
#01
10
Backdoor key access enabled
#10
11
Backdoor key access disabled
#11
MEEN
Mass Erase Enable
4
2
read-only
00
Mass erase is enabled
#00
01
Mass erase is enabled
#01
10
Mass erase is disabled
#10
11
Mass erase is enabled
#11
SEC
Flash Security
0
2
read-only
00
MCU security status is secure.
#00
01
MCU security status is secure.
#01
10
MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)
#10
11
MCU security status is secure.
#11
FSTAT
Flash Status Register
0x0
8
read-write
n
0x0
0x0
ACCERR
Flash Access Error Flag
5
1
read-write
0
No access error detected
#0
1
Access error detected
#1
CCIF
Command Complete Interrupt Flag
7
1
read-write
0
Flash command in progress
#0
1
Flash command has completed
#1
FPVIOL
Flash Protection Violation Flag
4
1
read-write
0
No protection violation detected
#0
1
Protection violation detected
#1
MGSTAT0
Memory Controller Command Completion Status Flag
0
1
read-only
RDCOLERR
Flash Read Collision Error Flag
6
1
read-write
0
No collision error detected
#0
1
Collision error detected
#1
FTFA_FlashConfig
Flash configuration field
FTFA_FlashConfig
0x0
0x0
0xE
registers
n
NV_BACKKEY0
Backdoor Comparison Key 0.
0x3
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY1
Backdoor Comparison Key 1.
0x2
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY2
Backdoor Comparison Key 2.
0x1
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY3
Backdoor Comparison Key 3.
0x0
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY4
Backdoor Comparison Key 4.
0x7
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY5
Backdoor Comparison Key 5.
0x6
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY6
Backdoor Comparison Key 6.
0x5
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY7
Backdoor Comparison Key 7.
0x4
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_FOPT
Non-volatile Flash Option Register
0xD
8
read-only
n
0x0
0x0
BOOTPIN_OPT
no description available
1
1
read-only
0
Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin
#0
1
Boot source configured by FOPT (BOOTSRC_SEL) bits
#1
BOOTSRC_SEL
Boot source selection
6
2
read-only
00
Boot from Flash
#00
10
Boot from ROM
#10
11
Boot from ROM
#11
FAST_INIT
no description available
5
1
read-only
0
Slower initialization
#0
1
Fast Initialization
#1
LPBOOT0
no description available
0
1
read-only
0
Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1.
#0
1
Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1.
#1
LPBOOT1
no description available
4
1
read-only
0
Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1.
#0
1
Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1.
#1
NMI_DIS
no description available
2
1
read-only
0
NMI interrupts are always blocked
#0
1
NMI_b pin/interrupts reset default to enabled
#1
RESET_PIN_CFG
no description available
3
1
read-only
0
RESET pin is disabled following a POR and cannot be enabled as reset function
#0
1
RESET_b pin is dedicated
#1
NV_FPROT0
Non-volatile P-Flash Protection 0 - High Register
0xB
8
read-only
n
0x0
0x0
PROT
P-Flash Region Protect
0
8
read-only
NV_FPROT1
Non-volatile P-Flash Protection 0 - Low Register
0xA
8
read-only
n
0x0
0x0
PROT
P-Flash Region Protect
0
8
read-only
NV_FPROT2
Non-volatile P-Flash Protection 1 - High Register
0x9
8
read-only
n
0x0
0x0
PROT
P-Flash Region Protect
0
8
read-only
NV_FPROT3
Non-volatile P-Flash Protection 1 - Low Register
0x8
8
read-only
n
0x0
0x0
PROT
P-Flash Region Protect
0
8
read-only
NV_FSEC
Non-volatile Flash Security Register
0xC
8
read-only
n
0x0
0x0
FSLACC
Freescale Failure Analysis Access Code
2
2
read-only
10
Freescale factory access denied
#10
11
Freescale factory access granted
#11
KEYEN
Backdoor Key Security Enable
6
2
read-only
10
Backdoor key access enabled
#10
11
Backdoor key access disabled
#11
MEEN
no description available
4
2
read-only
10
Mass erase is disabled
#10
11
Mass erase is enabled
#11
SEC
Flash Security
0
2
read-only
10
MCU security status is unsecure
#10
11
MCU security status is secure
#11
GPIOA
General Purpose Input/Output
GPIO
0x0
0x0
0x18
registers
n
PORTA
30
PCOR
Port Clear Output Register
0x8
32
read-write
n
0x0
0x0
PTCO0
Port Clear Output
0
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO1
Port Clear Output
1
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO10
Port Clear Output
10
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO11
Port Clear Output
11
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO12
Port Clear Output
12
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO13
Port Clear Output
13
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO14
Port Clear Output
14
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO15
Port Clear Output
15
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO16
Port Clear Output
16
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO17
Port Clear Output
17
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO18
Port Clear Output
18
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO19
Port Clear Output
19
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO2
Port Clear Output
2
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO20
Port Clear Output
20
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO21
Port Clear Output
21
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO22
Port Clear Output
22
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO23
Port Clear Output
23
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO24
Port Clear Output
24
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO25
Port Clear Output
25
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO26
Port Clear Output
26
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO27
Port Clear Output
27
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO28
Port Clear Output
28
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO29
Port Clear Output
29
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO3
Port Clear Output
3
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO30
Port Clear Output
30
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO31
Port Clear Output
31
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO4
Port Clear Output
4
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO5
Port Clear Output
5
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO6
Port Clear Output
6
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO7
Port Clear Output
7
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO8
Port Clear Output
8
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO9
Port Clear Output
9
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD0
Port Data Direction
0
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD1
Port Data Direction
1
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD10
Port Data Direction
10
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD11
Port Data Direction
11
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD12
Port Data Direction
12
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD13
Port Data Direction
13
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD14
Port Data Direction
14
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD15
Port Data Direction
15
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD16
Port Data Direction
16
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD17
Port Data Direction
17
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD18
Port Data Direction
18
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD19
Port Data Direction
19
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD2
Port Data Direction
2
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD20
Port Data Direction
20
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD21
Port Data Direction
21
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD22
Port Data Direction
22
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD23
Port Data Direction
23
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD24
Port Data Direction
24
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD25
Port Data Direction
25
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD26
Port Data Direction
26
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD27
Port Data Direction
27
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD28
Port Data Direction
28
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD29
Port Data Direction
29
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD3
Port Data Direction
3
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD30
Port Data Direction
30
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD31
Port Data Direction
31
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD4
Port Data Direction
4
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD5
Port Data Direction
5
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD6
Port Data Direction
6
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD7
Port Data Direction
7
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD8
Port Data Direction
8
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD9
Port Data Direction
9
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI0
Port Data Input
0
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI1
Port Data Input
1
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI10
Port Data Input
10
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI11
Port Data Input
11
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI12
Port Data Input
12
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI13
Port Data Input
13
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI14
Port Data Input
14
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI15
Port Data Input
15
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI16
Port Data Input
16
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI17
Port Data Input
17
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI18
Port Data Input
18
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI19
Port Data Input
19
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI2
Port Data Input
2
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI20
Port Data Input
20
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI21
Port Data Input
21
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI22
Port Data Input
22
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI23
Port Data Input
23
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI24
Port Data Input
24
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI25
Port Data Input
25
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI26
Port Data Input
26
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI27
Port Data Input
27
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI28
Port Data Input
28
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI29
Port Data Input
29
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI3
Port Data Input
3
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI30
Port Data Input
30
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI31
Port Data Input
31
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI4
Port Data Input
4
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI5
Port Data Input
5
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI6
Port Data Input
6
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI7
Port Data Input
7
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI8
Port Data Input
8
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI9
Port Data Input
9
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO0
Port Data Output
0
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO1
Port Data Output
1
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO10
Port Data Output
10
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO11
Port Data Output
11
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO12
Port Data Output
12
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO13
Port Data Output
13
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO14
Port Data Output
14
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO15
Port Data Output
15
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO16
Port Data Output
16
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO17
Port Data Output
17
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO18
Port Data Output
18
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO19
Port Data Output
19
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO2
Port Data Output
2
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO20
Port Data Output
20
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO21
Port Data Output
21
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO22
Port Data Output
22
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO23
Port Data Output
23
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO24
Port Data Output
24
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO25
Port Data Output
25
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO26
Port Data Output
26
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO27
Port Data Output
27
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO28
Port Data Output
28
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO29
Port Data Output
29
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO3
Port Data Output
3
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO30
Port Data Output
30
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO31
Port Data Output
31
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO4
Port Data Output
4
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO5
Port Data Output
5
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO6
Port Data Output
6
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO7
Port Data Output
7
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO8
Port Data Output
8
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO9
Port Data Output
9
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
read-write
n
0x0
0x0
PTSO0
Port Set Output
0
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO1
Port Set Output
1
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO10
Port Set Output
10
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO11
Port Set Output
11
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO12
Port Set Output
12
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO13
Port Set Output
13
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO14
Port Set Output
14
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO15
Port Set Output
15
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO16
Port Set Output
16
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO17
Port Set Output
17
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO18
Port Set Output
18
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO19
Port Set Output
19
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO2
Port Set Output
2
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO20
Port Set Output
20
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO21
Port Set Output
21
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO22
Port Set Output
22
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO23
Port Set Output
23
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO24
Port Set Output
24
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO25
Port Set Output
25
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO26
Port Set Output
26
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO27
Port Set Output
27
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO28
Port Set Output
28
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO29
Port Set Output
29
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO3
Port Set Output
3
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO30
Port Set Output
30
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO31
Port Set Output
31
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO4
Port Set Output
4
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO5
Port Set Output
5
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO6
Port Set Output
6
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO7
Port Set Output
7
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO8
Port Set Output
8
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO9
Port Set Output
9
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
read-write
n
0x0
0x0
PTTO0
Port Toggle Output
0
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO1
Port Toggle Output
1
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO10
Port Toggle Output
10
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO11
Port Toggle Output
11
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO12
Port Toggle Output
12
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO13
Port Toggle Output
13
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO14
Port Toggle Output
14
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO15
Port Toggle Output
15
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO16
Port Toggle Output
16
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO17
Port Toggle Output
17
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO18
Port Toggle Output
18
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO19
Port Toggle Output
19
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO2
Port Toggle Output
2
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO20
Port Toggle Output
20
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO21
Port Toggle Output
21
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO22
Port Toggle Output
22
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO23
Port Toggle Output
23
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO24
Port Toggle Output
24
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO25
Port Toggle Output
25
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO26
Port Toggle Output
26
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO27
Port Toggle Output
27
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO28
Port Toggle Output
28
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO29
Port Toggle Output
29
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO3
Port Toggle Output
3
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO30
Port Toggle Output
30
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO31
Port Toggle Output
31
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO4
Port Toggle Output
4
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO5
Port Toggle Output
5
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO6
Port Toggle Output
6
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO7
Port Toggle Output
7
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO8
Port Toggle Output
8
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO9
Port Toggle Output
9
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
GPIOB
General Purpose Input/Output
GPIO
0x0
0x0
0x18
registers
n
PCOR
Port Clear Output Register
0x8
32
read-write
n
0x0
0x0
PTCO0
Port Clear Output
0
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO1
Port Clear Output
1
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO10
Port Clear Output
10
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO11
Port Clear Output
11
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO12
Port Clear Output
12
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO13
Port Clear Output
13
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO14
Port Clear Output
14
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO15
Port Clear Output
15
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO16
Port Clear Output
16
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO17
Port Clear Output
17
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO18
Port Clear Output
18
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO19
Port Clear Output
19
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO2
Port Clear Output
2
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO20
Port Clear Output
20
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO21
Port Clear Output
21
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO22
Port Clear Output
22
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO23
Port Clear Output
23
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO24
Port Clear Output
24
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO25
Port Clear Output
25
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO26
Port Clear Output
26
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO27
Port Clear Output
27
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO28
Port Clear Output
28
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO29
Port Clear Output
29
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO3
Port Clear Output
3
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO30
Port Clear Output
30
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO31
Port Clear Output
31
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO4
Port Clear Output
4
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO5
Port Clear Output
5
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO6
Port Clear Output
6
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO7
Port Clear Output
7
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO8
Port Clear Output
8
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO9
Port Clear Output
9
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD0
Port Data Direction
0
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD1
Port Data Direction
1
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD10
Port Data Direction
10
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD11
Port Data Direction
11
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD12
Port Data Direction
12
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD13
Port Data Direction
13
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD14
Port Data Direction
14
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD15
Port Data Direction
15
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD16
Port Data Direction
16
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD17
Port Data Direction
17
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD18
Port Data Direction
18
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD19
Port Data Direction
19
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD2
Port Data Direction
2
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD20
Port Data Direction
20
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD21
Port Data Direction
21
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD22
Port Data Direction
22
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD23
Port Data Direction
23
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD24
Port Data Direction
24
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD25
Port Data Direction
25
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD26
Port Data Direction
26
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD27
Port Data Direction
27
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD28
Port Data Direction
28
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD29
Port Data Direction
29
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD3
Port Data Direction
3
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD30
Port Data Direction
30
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD31
Port Data Direction
31
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD4
Port Data Direction
4
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD5
Port Data Direction
5
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD6
Port Data Direction
6
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD7
Port Data Direction
7
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD8
Port Data Direction
8
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD9
Port Data Direction
9
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI0
Port Data Input
0
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI1
Port Data Input
1
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI10
Port Data Input
10
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI11
Port Data Input
11
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI12
Port Data Input
12
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI13
Port Data Input
13
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI14
Port Data Input
14
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI15
Port Data Input
15
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI16
Port Data Input
16
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI17
Port Data Input
17
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI18
Port Data Input
18
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI19
Port Data Input
19
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI2
Port Data Input
2
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI20
Port Data Input
20
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI21
Port Data Input
21
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI22
Port Data Input
22
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI23
Port Data Input
23
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI24
Port Data Input
24
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI25
Port Data Input
25
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI26
Port Data Input
26
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI27
Port Data Input
27
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI28
Port Data Input
28
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI29
Port Data Input
29
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI3
Port Data Input
3
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI30
Port Data Input
30
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI31
Port Data Input
31
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI4
Port Data Input
4
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI5
Port Data Input
5
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI6
Port Data Input
6
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI7
Port Data Input
7
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI8
Port Data Input
8
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI9
Port Data Input
9
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO0
Port Data Output
0
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO1
Port Data Output
1
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO10
Port Data Output
10
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO11
Port Data Output
11
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO12
Port Data Output
12
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO13
Port Data Output
13
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO14
Port Data Output
14
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO15
Port Data Output
15
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO16
Port Data Output
16
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO17
Port Data Output
17
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO18
Port Data Output
18
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO19
Port Data Output
19
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO2
Port Data Output
2
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO20
Port Data Output
20
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO21
Port Data Output
21
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO22
Port Data Output
22
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO23
Port Data Output
23
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO24
Port Data Output
24
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO25
Port Data Output
25
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO26
Port Data Output
26
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO27
Port Data Output
27
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO28
Port Data Output
28
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO29
Port Data Output
29
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO3
Port Data Output
3
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO30
Port Data Output
30
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO31
Port Data Output
31
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO4
Port Data Output
4
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO5
Port Data Output
5
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO6
Port Data Output
6
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO7
Port Data Output
7
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO8
Port Data Output
8
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO9
Port Data Output
9
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
read-write
n
0x0
0x0
PTSO0
Port Set Output
0
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO1
Port Set Output
1
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO10
Port Set Output
10
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO11
Port Set Output
11
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO12
Port Set Output
12
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO13
Port Set Output
13
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO14
Port Set Output
14
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO15
Port Set Output
15
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO16
Port Set Output
16
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO17
Port Set Output
17
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO18
Port Set Output
18
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO19
Port Set Output
19
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO2
Port Set Output
2
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO20
Port Set Output
20
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO21
Port Set Output
21
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO22
Port Set Output
22
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO23
Port Set Output
23
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO24
Port Set Output
24
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO25
Port Set Output
25
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO26
Port Set Output
26
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO27
Port Set Output
27
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO28
Port Set Output
28
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO29
Port Set Output
29
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO3
Port Set Output
3
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO30
Port Set Output
30
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO31
Port Set Output
31
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO4
Port Set Output
4
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO5
Port Set Output
5
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO6
Port Set Output
6
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO7
Port Set Output
7
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO8
Port Set Output
8
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO9
Port Set Output
9
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
read-write
n
0x0
0x0
PTTO0
Port Toggle Output
0
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO1
Port Toggle Output
1
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO10
Port Toggle Output
10
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO11
Port Toggle Output
11
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO12
Port Toggle Output
12
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO13
Port Toggle Output
13
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO14
Port Toggle Output
14
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO15
Port Toggle Output
15
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO16
Port Toggle Output
16
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO17
Port Toggle Output
17
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO18
Port Toggle Output
18
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO19
Port Toggle Output
19
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO2
Port Toggle Output
2
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO20
Port Toggle Output
20
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO21
Port Toggle Output
21
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO22
Port Toggle Output
22
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO23
Port Toggle Output
23
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO24
Port Toggle Output
24
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO25
Port Toggle Output
25
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO26
Port Toggle Output
26
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO27
Port Toggle Output
27
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO28
Port Toggle Output
28
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO29
Port Toggle Output
29
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO3
Port Toggle Output
3
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO30
Port Toggle Output
30
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO31
Port Toggle Output
31
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO4
Port Toggle Output
4
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO5
Port Toggle Output
5
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO6
Port Toggle Output
6
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO7
Port Toggle Output
7
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO8
Port Toggle Output
8
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO9
Port Toggle Output
9
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
GPIOC
General Purpose Input/Output
GPIO
0x0
0x0
0x18
registers
n
PORTC_PORTD
31
PCOR
Port Clear Output Register
0x8
32
read-write
n
0x0
0x0
PTCO0
Port Clear Output
0
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO1
Port Clear Output
1
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO10
Port Clear Output
10
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO11
Port Clear Output
11
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO12
Port Clear Output
12
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO13
Port Clear Output
13
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO14
Port Clear Output
14
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO15
Port Clear Output
15
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO16
Port Clear Output
16
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO17
Port Clear Output
17
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO18
Port Clear Output
18
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO19
Port Clear Output
19
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO2
Port Clear Output
2
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO20
Port Clear Output
20
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO21
Port Clear Output
21
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO22
Port Clear Output
22
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO23
Port Clear Output
23
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO24
Port Clear Output
24
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO25
Port Clear Output
25
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO26
Port Clear Output
26
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO27
Port Clear Output
27
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO28
Port Clear Output
28
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO29
Port Clear Output
29
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO3
Port Clear Output
3
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO30
Port Clear Output
30
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO31
Port Clear Output
31
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO4
Port Clear Output
4
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO5
Port Clear Output
5
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO6
Port Clear Output
6
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO7
Port Clear Output
7
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO8
Port Clear Output
8
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO9
Port Clear Output
9
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD0
Port Data Direction
0
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD1
Port Data Direction
1
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD10
Port Data Direction
10
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD11
Port Data Direction
11
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD12
Port Data Direction
12
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD13
Port Data Direction
13
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD14
Port Data Direction
14
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD15
Port Data Direction
15
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD16
Port Data Direction
16
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD17
Port Data Direction
17
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD18
Port Data Direction
18
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD19
Port Data Direction
19
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD2
Port Data Direction
2
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD20
Port Data Direction
20
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD21
Port Data Direction
21
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD22
Port Data Direction
22
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD23
Port Data Direction
23
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD24
Port Data Direction
24
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD25
Port Data Direction
25
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD26
Port Data Direction
26
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD27
Port Data Direction
27
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD28
Port Data Direction
28
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD29
Port Data Direction
29
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD3
Port Data Direction
3
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD30
Port Data Direction
30
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD31
Port Data Direction
31
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD4
Port Data Direction
4
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD5
Port Data Direction
5
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD6
Port Data Direction
6
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD7
Port Data Direction
7
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD8
Port Data Direction
8
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD9
Port Data Direction
9
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI0
Port Data Input
0
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI1
Port Data Input
1
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI10
Port Data Input
10
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI11
Port Data Input
11
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI12
Port Data Input
12
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI13
Port Data Input
13
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI14
Port Data Input
14
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI15
Port Data Input
15
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI16
Port Data Input
16
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI17
Port Data Input
17
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI18
Port Data Input
18
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI19
Port Data Input
19
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI2
Port Data Input
2
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI20
Port Data Input
20
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI21
Port Data Input
21
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI22
Port Data Input
22
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI23
Port Data Input
23
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI24
Port Data Input
24
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI25
Port Data Input
25
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI26
Port Data Input
26
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI27
Port Data Input
27
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI28
Port Data Input
28
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI29
Port Data Input
29
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI3
Port Data Input
3
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI30
Port Data Input
30
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI31
Port Data Input
31
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI4
Port Data Input
4
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI5
Port Data Input
5
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI6
Port Data Input
6
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI7
Port Data Input
7
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI8
Port Data Input
8
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI9
Port Data Input
9
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO0
Port Data Output
0
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO1
Port Data Output
1
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO10
Port Data Output
10
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO11
Port Data Output
11
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO12
Port Data Output
12
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO13
Port Data Output
13
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO14
Port Data Output
14
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO15
Port Data Output
15
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO16
Port Data Output
16
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO17
Port Data Output
17
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO18
Port Data Output
18
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO19
Port Data Output
19
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO2
Port Data Output
2
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO20
Port Data Output
20
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO21
Port Data Output
21
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO22
Port Data Output
22
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO23
Port Data Output
23
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO24
Port Data Output
24
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO25
Port Data Output
25
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO26
Port Data Output
26
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO27
Port Data Output
27
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO28
Port Data Output
28
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO29
Port Data Output
29
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO3
Port Data Output
3
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO30
Port Data Output
30
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO31
Port Data Output
31
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO4
Port Data Output
4
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO5
Port Data Output
5
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO6
Port Data Output
6
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO7
Port Data Output
7
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO8
Port Data Output
8
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO9
Port Data Output
9
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
read-write
n
0x0
0x0
PTSO0
Port Set Output
0
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO1
Port Set Output
1
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO10
Port Set Output
10
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO11
Port Set Output
11
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO12
Port Set Output
12
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO13
Port Set Output
13
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO14
Port Set Output
14
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO15
Port Set Output
15
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO16
Port Set Output
16
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO17
Port Set Output
17
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO18
Port Set Output
18
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO19
Port Set Output
19
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO2
Port Set Output
2
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO20
Port Set Output
20
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO21
Port Set Output
21
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO22
Port Set Output
22
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO23
Port Set Output
23
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO24
Port Set Output
24
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO25
Port Set Output
25
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO26
Port Set Output
26
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO27
Port Set Output
27
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO28
Port Set Output
28
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO29
Port Set Output
29
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO3
Port Set Output
3
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO30
Port Set Output
30
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO31
Port Set Output
31
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO4
Port Set Output
4
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO5
Port Set Output
5
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO6
Port Set Output
6
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO7
Port Set Output
7
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO8
Port Set Output
8
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO9
Port Set Output
9
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
read-write
n
0x0
0x0
PTTO0
Port Toggle Output
0
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO1
Port Toggle Output
1
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO10
Port Toggle Output
10
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO11
Port Toggle Output
11
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO12
Port Toggle Output
12
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO13
Port Toggle Output
13
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO14
Port Toggle Output
14
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO15
Port Toggle Output
15
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO16
Port Toggle Output
16
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO17
Port Toggle Output
17
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO18
Port Toggle Output
18
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO19
Port Toggle Output
19
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO2
Port Toggle Output
2
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO20
Port Toggle Output
20
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO21
Port Toggle Output
21
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO22
Port Toggle Output
22
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO23
Port Toggle Output
23
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO24
Port Toggle Output
24
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO25
Port Toggle Output
25
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO26
Port Toggle Output
26
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO27
Port Toggle Output
27
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO28
Port Toggle Output
28
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO29
Port Toggle Output
29
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO3
Port Toggle Output
3
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO30
Port Toggle Output
30
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO31
Port Toggle Output
31
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO4
Port Toggle Output
4
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO5
Port Toggle Output
5
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO6
Port Toggle Output
6
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO7
Port Toggle Output
7
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO8
Port Toggle Output
8
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO9
Port Toggle Output
9
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
GPIOD
General Purpose Input/Output
GPIO
0x0
0x0
0x18
registers
n
PORTC_PORTD
31
PCOR
Port Clear Output Register
0x8
32
read-write
n
0x0
0x0
PTCO0
Port Clear Output
0
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO1
Port Clear Output
1
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO10
Port Clear Output
10
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO11
Port Clear Output
11
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO12
Port Clear Output
12
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO13
Port Clear Output
13
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO14
Port Clear Output
14
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO15
Port Clear Output
15
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO16
Port Clear Output
16
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO17
Port Clear Output
17
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO18
Port Clear Output
18
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO19
Port Clear Output
19
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO2
Port Clear Output
2
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO20
Port Clear Output
20
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO21
Port Clear Output
21
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO22
Port Clear Output
22
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO23
Port Clear Output
23
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO24
Port Clear Output
24
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO25
Port Clear Output
25
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO26
Port Clear Output
26
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO27
Port Clear Output
27
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO28
Port Clear Output
28
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO29
Port Clear Output
29
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO3
Port Clear Output
3
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO30
Port Clear Output
30
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO31
Port Clear Output
31
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO4
Port Clear Output
4
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO5
Port Clear Output
5
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO6
Port Clear Output
6
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO7
Port Clear Output
7
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO8
Port Clear Output
8
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO9
Port Clear Output
9
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD0
Port Data Direction
0
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD1
Port Data Direction
1
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD10
Port Data Direction
10
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD11
Port Data Direction
11
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD12
Port Data Direction
12
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD13
Port Data Direction
13
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD14
Port Data Direction
14
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD15
Port Data Direction
15
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD16
Port Data Direction
16
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD17
Port Data Direction
17
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD18
Port Data Direction
18
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD19
Port Data Direction
19
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD2
Port Data Direction
2
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD20
Port Data Direction
20
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD21
Port Data Direction
21
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD22
Port Data Direction
22
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD23
Port Data Direction
23
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD24
Port Data Direction
24
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD25
Port Data Direction
25
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD26
Port Data Direction
26
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD27
Port Data Direction
27
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD28
Port Data Direction
28
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD29
Port Data Direction
29
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD3
Port Data Direction
3
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD30
Port Data Direction
30
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD31
Port Data Direction
31
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD4
Port Data Direction
4
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD5
Port Data Direction
5
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD6
Port Data Direction
6
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD7
Port Data Direction
7
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD8
Port Data Direction
8
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD9
Port Data Direction
9
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI0
Port Data Input
0
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI1
Port Data Input
1
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI10
Port Data Input
10
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI11
Port Data Input
11
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI12
Port Data Input
12
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI13
Port Data Input
13
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI14
Port Data Input
14
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI15
Port Data Input
15
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI16
Port Data Input
16
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI17
Port Data Input
17
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI18
Port Data Input
18
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI19
Port Data Input
19
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI2
Port Data Input
2
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI20
Port Data Input
20
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI21
Port Data Input
21
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI22
Port Data Input
22
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI23
Port Data Input
23
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI24
Port Data Input
24
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI25
Port Data Input
25
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI26
Port Data Input
26
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI27
Port Data Input
27
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI28
Port Data Input
28
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI29
Port Data Input
29
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI3
Port Data Input
3
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI30
Port Data Input
30
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI31
Port Data Input
31
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI4
Port Data Input
4
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI5
Port Data Input
5
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI6
Port Data Input
6
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI7
Port Data Input
7
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI8
Port Data Input
8
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI9
Port Data Input
9
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO0
Port Data Output
0
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO1
Port Data Output
1
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO10
Port Data Output
10
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO11
Port Data Output
11
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO12
Port Data Output
12
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO13
Port Data Output
13
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO14
Port Data Output
14
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO15
Port Data Output
15
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO16
Port Data Output
16
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO17
Port Data Output
17
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO18
Port Data Output
18
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO19
Port Data Output
19
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO2
Port Data Output
2
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO20
Port Data Output
20
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO21
Port Data Output
21
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO22
Port Data Output
22
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO23
Port Data Output
23
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO24
Port Data Output
24
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO25
Port Data Output
25
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO26
Port Data Output
26
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO27
Port Data Output
27
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO28
Port Data Output
28
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO29
Port Data Output
29
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO3
Port Data Output
3
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO30
Port Data Output
30
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO31
Port Data Output
31
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO4
Port Data Output
4
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO5
Port Data Output
5
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO6
Port Data Output
6
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO7
Port Data Output
7
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO8
Port Data Output
8
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO9
Port Data Output
9
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
read-write
n
0x0
0x0
PTSO0
Port Set Output
0
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO1
Port Set Output
1
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO10
Port Set Output
10
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO11
Port Set Output
11
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO12
Port Set Output
12
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO13
Port Set Output
13
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO14
Port Set Output
14
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO15
Port Set Output
15
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO16
Port Set Output
16
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO17
Port Set Output
17
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO18
Port Set Output
18
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO19
Port Set Output
19
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO2
Port Set Output
2
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO20
Port Set Output
20
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO21
Port Set Output
21
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO22
Port Set Output
22
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO23
Port Set Output
23
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO24
Port Set Output
24
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO25
Port Set Output
25
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO26
Port Set Output
26
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO27
Port Set Output
27
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO28
Port Set Output
28
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO29
Port Set Output
29
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO3
Port Set Output
3
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO30
Port Set Output
30
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO31
Port Set Output
31
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO4
Port Set Output
4
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO5
Port Set Output
5
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO6
Port Set Output
6
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO7
Port Set Output
7
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO8
Port Set Output
8
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO9
Port Set Output
9
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
read-write
n
0x0
0x0
PTTO0
Port Toggle Output
0
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO1
Port Toggle Output
1
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO10
Port Toggle Output
10
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO11
Port Toggle Output
11
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO12
Port Toggle Output
12
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO13
Port Toggle Output
13
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO14
Port Toggle Output
14
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO15
Port Toggle Output
15
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO16
Port Toggle Output
16
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO17
Port Toggle Output
17
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO18
Port Toggle Output
18
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO19
Port Toggle Output
19
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO2
Port Toggle Output
2
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO20
Port Toggle Output
20
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO21
Port Toggle Output
21
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO22
Port Toggle Output
22
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO23
Port Toggle Output
23
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO24
Port Toggle Output
24
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO25
Port Toggle Output
25
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO26
Port Toggle Output
26
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO27
Port Toggle Output
27
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO28
Port Toggle Output
28
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO29
Port Toggle Output
29
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO3
Port Toggle Output
3
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO30
Port Toggle Output
30
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO31
Port Toggle Output
31
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO4
Port Toggle Output
4
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO5
Port Toggle Output
5
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO6
Port Toggle Output
6
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO7
Port Toggle Output
7
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO8
Port Toggle Output
8
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO9
Port Toggle Output
9
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
GPIOE
General Purpose Input/Output
GPIO
0x0
0x0
0x18
registers
n
PCOR
Port Clear Output Register
0x8
32
read-write
n
0x0
0x0
PTCO0
Port Clear Output
0
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO1
Port Clear Output
1
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO10
Port Clear Output
10
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO11
Port Clear Output
11
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO12
Port Clear Output
12
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO13
Port Clear Output
13
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO14
Port Clear Output
14
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO15
Port Clear Output
15
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO16
Port Clear Output
16
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO17
Port Clear Output
17
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO18
Port Clear Output
18
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO19
Port Clear Output
19
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO2
Port Clear Output
2
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO20
Port Clear Output
20
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO21
Port Clear Output
21
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO22
Port Clear Output
22
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO23
Port Clear Output
23
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO24
Port Clear Output
24
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO25
Port Clear Output
25
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO26
Port Clear Output
26
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO27
Port Clear Output
27
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO28
Port Clear Output
28
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO29
Port Clear Output
29
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO3
Port Clear Output
3
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO30
Port Clear Output
30
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO31
Port Clear Output
31
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO4
Port Clear Output
4
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO5
Port Clear Output
5
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO6
Port Clear Output
6
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO7
Port Clear Output
7
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO8
Port Clear Output
8
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PTCO9
Port Clear Output
9
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD0
Port Data Direction
0
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD1
Port Data Direction
1
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD10
Port Data Direction
10
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD11
Port Data Direction
11
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD12
Port Data Direction
12
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD13
Port Data Direction
13
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD14
Port Data Direction
14
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD15
Port Data Direction
15
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD16
Port Data Direction
16
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD17
Port Data Direction
17
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD18
Port Data Direction
18
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD19
Port Data Direction
19
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD2
Port Data Direction
2
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD20
Port Data Direction
20
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD21
Port Data Direction
21
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD22
Port Data Direction
22
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD23
Port Data Direction
23
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD24
Port Data Direction
24
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD25
Port Data Direction
25
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD26
Port Data Direction
26
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD27
Port Data Direction
27
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD28
Port Data Direction
28
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD29
Port Data Direction
29
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD3
Port Data Direction
3
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD30
Port Data Direction
30
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD31
Port Data Direction
31
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD4
Port Data Direction
4
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD5
Port Data Direction
5
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD6
Port Data Direction
6
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD7
Port Data Direction
7
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD8
Port Data Direction
8
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDD9
Port Data Direction
9
1
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI0
Port Data Input
0
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI1
Port Data Input
1
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI10
Port Data Input
10
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI11
Port Data Input
11
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI12
Port Data Input
12
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI13
Port Data Input
13
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI14
Port Data Input
14
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI15
Port Data Input
15
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI16
Port Data Input
16
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI17
Port Data Input
17
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI18
Port Data Input
18
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI19
Port Data Input
19
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI2
Port Data Input
2
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI20
Port Data Input
20
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI21
Port Data Input
21
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI22
Port Data Input
22
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI23
Port Data Input
23
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI24
Port Data Input
24
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI25
Port Data Input
25
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI26
Port Data Input
26
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI27
Port Data Input
27
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI28
Port Data Input
28
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI29
Port Data Input
29
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI3
Port Data Input
3
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI30
Port Data Input
30
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI31
Port Data Input
31
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI4
Port Data Input
4
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI5
Port Data Input
5
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI6
Port Data Input
6
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI7
Port Data Input
7
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI8
Port Data Input
8
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDI9
Port Data Input
9
1
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO0
Port Data Output
0
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO1
Port Data Output
1
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO10
Port Data Output
10
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO11
Port Data Output
11
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO12
Port Data Output
12
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO13
Port Data Output
13
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO14
Port Data Output
14
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO15
Port Data Output
15
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO16
Port Data Output
16
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO17
Port Data Output
17
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO18
Port Data Output
18
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO19
Port Data Output
19
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO2
Port Data Output
2
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO20
Port Data Output
20
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO21
Port Data Output
21
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO22
Port Data Output
22
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO23
Port Data Output
23
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO24
Port Data Output
24
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO25
Port Data Output
25
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO26
Port Data Output
26
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO27
Port Data Output
27
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO28
Port Data Output
28
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO29
Port Data Output
29
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO3
Port Data Output
3
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO30
Port Data Output
30
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO31
Port Data Output
31
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO4
Port Data Output
4
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO5
Port Data Output
5
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO6
Port Data Output
6
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO7
Port Data Output
7
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO8
Port Data Output
8
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PDO9
Port Data Output
9
1
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
read-write
n
0x0
0x0
PTSO0
Port Set Output
0
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO1
Port Set Output
1
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO10
Port Set Output
10
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO11
Port Set Output
11
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO12
Port Set Output
12
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO13
Port Set Output
13
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO14
Port Set Output
14
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO15
Port Set Output
15
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO16
Port Set Output
16
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO17
Port Set Output
17
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO18
Port Set Output
18
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO19
Port Set Output
19
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO2
Port Set Output
2
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO20
Port Set Output
20
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO21
Port Set Output
21
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO22
Port Set Output
22
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO23
Port Set Output
23
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO24
Port Set Output
24
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO25
Port Set Output
25
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO26
Port Set Output
26
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO27
Port Set Output
27
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO28
Port Set Output
28
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO29
Port Set Output
29
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO3
Port Set Output
3
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO30
Port Set Output
30
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO31
Port Set Output
31
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO4
Port Set Output
4
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO5
Port Set Output
5
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO6
Port Set Output
6
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO7
Port Set Output
7
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO8
Port Set Output
8
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTSO9
Port Set Output
9
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
read-write
n
0x0
0x0
PTTO0
Port Toggle Output
0
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO1
Port Toggle Output
1
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO10
Port Toggle Output
10
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO11
Port Toggle Output
11
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO12
Port Toggle Output
12
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO13
Port Toggle Output
13
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO14
Port Toggle Output
14
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO15
Port Toggle Output
15
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO16
Port Toggle Output
16
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO17
Port Toggle Output
17
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO18
Port Toggle Output
18
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO19
Port Toggle Output
19
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO2
Port Toggle Output
2
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO20
Port Toggle Output
20
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO21
Port Toggle Output
21
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO22
Port Toggle Output
22
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO23
Port Toggle Output
23
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO24
Port Toggle Output
24
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO25
Port Toggle Output
25
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO26
Port Toggle Output
26
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO27
Port Toggle Output
27
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO28
Port Toggle Output
28
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO29
Port Toggle Output
29
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO3
Port Toggle Output
3
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO30
Port Toggle Output
30
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO31
Port Toggle Output
31
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO4
Port Toggle Output
4
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO5
Port Toggle Output
5
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO6
Port Toggle Output
6
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO7
Port Toggle Output
7
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO8
Port Toggle Output
8
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTTO9
Port Toggle Output
9
1
read-write
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
I2C0
Inter-Integrated Circuit
I2C
0x0
0x0
0xD
registers
n
I2C0
8
A1
I2C Address Register 1
0x0
8
read-write
n
0x0
0x0
AD
Address
1
7
read-write
A2
I2C Address Register 2
0x9
8
read-write
n
0x0
0x0
SAD
SMBus Address
1
7
read-write
C1
I2C Control Register 1
0x2
8
read-write
n
0x0
0x0
DMAEN
DMA Enable
0
1
read-write
0
All DMA signalling disabled.
#0
1
DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.
#1
IICEN
I2C Enable
7
1
read-write
0
Disabled
#0
1
Enabled
#1
IICIE
I2C Interrupt Enable
6
1
read-write
0
Disabled
#0
1
Enabled
#1
MST
Master Mode Select
5
1
read-write
0
Slave mode
#0
1
Master mode
#1
RSTA
Repeat START
2
1
read-write
TX
Transmit Mode Select
4
1
read-write
0
Receive
#0
1
Transmit
#1
TXAK
Transmit Acknowledge Enable
3
1
read-write
0
An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).
#0
1
No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).
#1
WUEN
Wakeup Enable
1
1
read-write
0
Normal operation. No interrupt generated when address matching in low power mode.
#0
1
Enables the wakeup function in low power mode.
#1
C2
I2C Control Register 2
0x5
8
read-write
n
0x0
0x0
AD
Slave Address
0
3
read-write
ADEXT
Address Extension
6
1
read-write
0
7-bit address scheme
#0
1
10-bit address scheme
#1
GCAEN
General Call Address Enable
7
1
read-write
0
Disabled
#0
1
Enabled
#1
HDRS
High Drive Select
5
1
read-write
0
Normal drive mode
#0
1
High drive mode
#1
RMEN
Range Address Matching Enable
3
1
read-write
0
Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.
#0
1
Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
#1
SBRC
Slave Baud Rate Control
4
1
read-write
0
The slave baud rate follows the master baud rate and clock stretching may occur
#0
1
Slave baud rate is independent of the master baud rate
#1
D
I2C Data I/O register
0x4
8
read-write
n
0x0
0x0
DATA
Data
0
8
read-write
F
I2C Frequency Divider register
0x1
8
read-write
n
0x0
0x0
ICR
ClockRate
0
6
read-write
MULT
Multiplier Factor
6
2
read-write
00
mul = 1
#00
01
mul = 2
#01
10
mul = 4
#10
FLT
I2C Programmable Input Glitch Filter Register
0x6
8
read-write
n
0x0
0x0
FLT
I2C Programmable Filter Factor
0
4
read-write
0
No filter/bypass
#0000
SHEN
Stop Hold Enable
7
1
read-write
0
Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
#0
1
Stop holdoff is enabled.
#1
SSIE
I2C Bus Stop or Start Interrupt Enable
5
1
read-write
0
Stop or start detection interrupt is disabled
#0
1
Stop or start detection interrupt is enabled
#1
STARTF
I2C Bus Start Detect Flag
4
1
read-write
0
No start happens on I2C bus
#0
1
Start detected on I2C bus
#1
STOPF
I2C Bus Stop Detect Flag
6
1
read-write
0
No stop happens on I2C bus
#0
1
Stop detected on I2C bus
#1
RA
I2C Range Address register
0x7
8
read-write
n
0x0
0x0
RAD
Range Slave Address
1
7
read-write
S
I2C Status register
0x3
8
read-write
n
0x0
0x0
ARBL
Arbitration Lost
4
1
read-write
0
Standard bus operation.
#0
1
Loss of arbitration.
#1
BUSY
Bus Busy
5
1
read-only
0
Bus is idle
#0
1
Bus is busy
#1
IAAS
Addressed As A Slave
6
1
read-write
0
Not addressed
#0
1
Addressed as a slave
#1
IICIF
Interrupt Flag
1
1
read-write
0
No interrupt pending
#0
1
Interrupt pending
#1
RAM
Range Address Match
3
1
read-write
0
Not addressed
#0
1
Addressed as a slave
#1
RXAK
Receive Acknowledge
0
1
read-only
0
Acknowledge signal was received after the completion of one byte of data transmission on the bus
#0
1
No acknowledge signal detected
#1
SRW
Slave Read/Write
2
1
read-only
0
Slave receive, master writing to slave
#0
1
Slave transmit, master reading from slave
#1
TCF
Transfer Complete Flag
7
1
read-only
0
Transfer in progress
#0
1
Transfer complete
#1
S2
I2C Status register 2
0xC
8
read-write
n
0x0
0x0
EMPTY
Empty flag
0
1
read-only
0
Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer.
#0
1
Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer.
#1
ERROR
Error flag
1
1
read-write
0
The buffer is not full and all write/read operations have no errors.
#0
1
There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set and the buffer is busy).
#1
SLTH
I2C SCL Low Timeout Register High
0xA
8
read-write
n
0x0
0x0
SSLT
SSLT[15:8]
0
8
read-write
SLTL
I2C SCL Low Timeout Register Low
0xB
8
read-write
n
0x0
0x0
SSLT
SSLT[7:0]
0
8
read-write
SMB
I2C SMBus Control and Status register
0x8
8
read-write
n
0x0
0x0
ALERTEN
SMBus Alert Response Address Enable
6
1
read-write
0
SMBus alert response address matching is disabled
#0
1
SMBus alert response address matching is enabled
#1
FACK
Fast NACK/ACK Enable
7
1
read-write
0
An ACK or NACK is sent on the following receiving data byte
#0
1
Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
#1
SHTF1
SCL High Timeout Flag 1
2
1
read-only
0
No SCL high and SDA high timeout occurs
#0
1
SCL high and SDA high timeout occurs
#1
SHTF2
SCL High Timeout Flag 2
1
1
read-write
0
No SCL high and SDA low timeout occurs
#0
1
SCL high and SDA low timeout occurs
#1
SHTF2IE
SHTF2 Interrupt Enable
0
1
read-write
0
SHTF2 interrupt is disabled
#0
1
SHTF2 interrupt is enabled
#1
SIICAEN
Second I2C Address Enable
5
1
read-write
0
I2C address register 2 matching is disabled
#0
1
I2C address register 2 matching is enabled
#1
SLTF
SCL Low Timeout Flag
3
1
read-write
0
No low timeout occurs
#0
1
Low timeout occurs
#1
TCKSEL
Timeout Counter Clock Select
4
1
read-write
0
Timeout counter counts at the frequency of the I2C module clock / 64
#0
1
Timeout counter counts at the frequency of the I2C module clock
#1
I2C1
Inter-Integrated Circuit
I2C
0x0
0x0
0xD
registers
n
I2C1
9
A1
I2C Address Register 1
0x0
8
read-write
n
0x0
0x0
AD
Address
1
7
read-write
A2
I2C Address Register 2
0x9
8
read-write
n
0x0
0x0
SAD
SMBus Address
1
7
read-write
C1
I2C Control Register 1
0x2
8
read-write
n
0x0
0x0
DMAEN
DMA Enable
0
1
read-write
0
All DMA signalling disabled.
#0
1
DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.
#1
IICEN
I2C Enable
7
1
read-write
0
Disabled
#0
1
Enabled
#1
IICIE
I2C Interrupt Enable
6
1
read-write
0
Disabled
#0
1
Enabled
#1
MST
Master Mode Select
5
1
read-write
0
Slave mode
#0
1
Master mode
#1
RSTA
Repeat START
2
1
read-write
TX
Transmit Mode Select
4
1
read-write
0
Receive
#0
1
Transmit
#1
TXAK
Transmit Acknowledge Enable
3
1
read-write
0
An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).
#0
1
No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).
#1
WUEN
Wakeup Enable
1
1
read-write
0
Normal operation. No interrupt generated when address matching in low power mode.
#0
1
Enables the wakeup function in low power mode.
#1
C2
I2C Control Register 2
0x5
8
read-write
n
0x0
0x0
AD
Slave Address
0
3
read-write
ADEXT
Address Extension
6
1
read-write
0
7-bit address scheme
#0
1
10-bit address scheme
#1
GCAEN
General Call Address Enable
7
1
read-write
0
Disabled
#0
1
Enabled
#1
HDRS
High Drive Select
5
1
read-write
0
Normal drive mode
#0
1
High drive mode
#1
RMEN
Range Address Matching Enable
3
1
read-write
0
Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.
#0
1
Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
#1
SBRC
Slave Baud Rate Control
4
1
read-write
0
The slave baud rate follows the master baud rate and clock stretching may occur
#0
1
Slave baud rate is independent of the master baud rate
#1
D
I2C Data I/O register
0x4
8
read-write
n
0x0
0x0
DATA
Data
0
8
read-write
F
I2C Frequency Divider register
0x1
8
read-write
n
0x0
0x0
ICR
ClockRate
0
6
read-write
MULT
Multiplier Factor
6
2
read-write
00
mul = 1
#00
01
mul = 2
#01
10
mul = 4
#10
FLT
I2C Programmable Input Glitch Filter Register
0x6
8
read-write
n
0x0
0x0
FLT
I2C Programmable Filter Factor
0
4
read-write
0
No filter/bypass
#0000
SHEN
Stop Hold Enable
7
1
read-write
0
Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
#0
1
Stop holdoff is enabled.
#1
SSIE
I2C Bus Stop or Start Interrupt Enable
5
1
read-write
0
Stop or start detection interrupt is disabled
#0
1
Stop or start detection interrupt is enabled
#1
STARTF
I2C Bus Start Detect Flag
4
1
read-write
0
No start happens on I2C bus
#0
1
Start detected on I2C bus
#1
STOPF
I2C Bus Stop Detect Flag
6
1
read-write
0
No stop happens on I2C bus
#0
1
Stop detected on I2C bus
#1
RA
I2C Range Address register
0x7
8
read-write
n
0x0
0x0
RAD
Range Slave Address
1
7
read-write
S
I2C Status register
0x3
8
read-write
n
0x0
0x0
ARBL
Arbitration Lost
4
1
read-write
0
Standard bus operation.
#0
1
Loss of arbitration.
#1
BUSY
Bus Busy
5
1
read-only
0
Bus is idle
#0
1
Bus is busy
#1
IAAS
Addressed As A Slave
6
1
read-write
0
Not addressed
#0
1
Addressed as a slave
#1
IICIF
Interrupt Flag
1
1
read-write
0
No interrupt pending
#0
1
Interrupt pending
#1
RAM
Range Address Match
3
1
read-write
0
Not addressed
#0
1
Addressed as a slave
#1
RXAK
Receive Acknowledge
0
1
read-only
0
Acknowledge signal was received after the completion of one byte of data transmission on the bus
#0
1
No acknowledge signal detected
#1
SRW
Slave Read/Write
2
1
read-only
0
Slave receive, master writing to slave
#0
1
Slave transmit, master reading from slave
#1
TCF
Transfer Complete Flag
7
1
read-only
0
Transfer in progress
#0
1
Transfer complete
#1
S2
I2C Status register 2
0xC
8
read-write
n
0x0
0x0
EMPTY
Empty flag
0
1
read-only
0
Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer.
#0
1
Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer.
#1
ERROR
Error flag
1
1
read-write
0
The buffer is not full and all write/read operations have no errors.
#0
1
There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set and the buffer is busy).
#1
SLTH
I2C SCL Low Timeout Register High
0xA
8
read-write
n
0x0
0x0
SSLT
SSLT[15:8]
0
8
read-write
SLTL
I2C SCL Low Timeout Register Low
0xB
8
read-write
n
0x0
0x0
SSLT
SSLT[7:0]
0
8
read-write
SMB
I2C SMBus Control and Status register
0x8
8
read-write
n
0x0
0x0
ALERTEN
SMBus Alert Response Address Enable
6
1
read-write
0
SMBus alert response address matching is disabled
#0
1
SMBus alert response address matching is enabled
#1
FACK
Fast NACK/ACK Enable
7
1
read-write
0
An ACK or NACK is sent on the following receiving data byte
#0
1
Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
#1
SHTF1
SCL High Timeout Flag 1
2
1
read-only
0
No SCL high and SDA high timeout occurs
#0
1
SCL high and SDA high timeout occurs
#1
SHTF2
SCL High Timeout Flag 2
1
1
read-write
0
No SCL high and SDA low timeout occurs
#0
1
SCL high and SDA low timeout occurs
#1
SHTF2IE
SHTF2 Interrupt Enable
0
1
read-write
0
SHTF2 interrupt is disabled
#0
1
SHTF2 interrupt is enabled
#1
SIICAEN
Second I2C Address Enable
5
1
read-write
0
I2C address register 2 matching is disabled
#0
1
I2C address register 2 matching is enabled
#1
SLTF
SCL Low Timeout Flag
3
1
read-write
0
No low timeout occurs
#0
1
Low timeout occurs
#1
TCKSEL
Timeout Counter Clock Select
4
1
read-write
0
Timeout counter counts at the frequency of the I2C module clock / 64
#0
1
Timeout counter counts at the frequency of the I2C module clock
#1
LCD
Segment Liquid Crystal Display
LCD
0x0
0x0
0x60
registers
n
LCD
29
AR
LCD Auxiliary Register
0x4
32
read-write
n
0x0
0x0
ALT
Alternate display mode
6
1
read-write
0
Normal display mode.
#0
1
Alternate display mode.
#1
BLANK
Blank display mode
5
1
read-write
0
Normal or alternate display mode.
#0
1
Blank display mode.
#1
BLINK
Blink command
7
1
read-write
0
Disables blinking.
#0
1
Starts blinking at blinking frequency specified by LCD blink rate calculation.
#1
BMODE
Blink mode
3
1
read-write
0
Display blank during the blink period.
#0
1
Display alternate display during blink period (Ignored if duty is 5 or greater).
#1
BRATE
Blink-rate configuration
0
3
read-write
BPENH
LCD Back Plane Enable register
0x4C
32
read-write
n
0x0
0x0
BPEN
Back Plane Enable
0
32
read-write
0
Front plane operation enabled on LCD_Pn.
#0
1
Back plane operation enabled on LCD_Pn.
#1
BPENL
LCD Back Plane Enable register
0x30
32
read-write
n
0x0
0x0
BPEN
Back Plane Enable
0
32
read-write
0
Front plane operation enabled on LCD_Pn.
#0
1
Back plane operation enabled on LCD_Pn.
#1
FDCR
LCD Fault Detect Control Register
0x8
32
read-write
n
0x0
0x0
FDBPEN
Fault Detect Back Plane Enable
6
1
read-write
0
Type of the selected pin under fault detect test is front plane.
#0
1
Type of the selected pin under fault detect test is back plane.
#1
FDEN
Fault Detect Enable
7
1
read-write
0
Disable fault detection.
#0
1
Enable fault detection.
#1
FDPINID
Fault Detect Pin ID
0
6
read-write
000000
Fault detection for LCD_P0 pin.
#0
000001
Fault detection for LCD_P1 pin.
#1
111111
Fault detection for LCD_P63 pin.
#111111
FDPRS
Fault Detect Clock Prescaler
12
3
read-write
000
1/1 bus clock.
#000
001
1/2 bus clock.
#001
010
1/4 bus clock.
#010
011
1/8 bus clock.
#011
100
1/16 bus clock.
#100
101
1/32 bus clock.
#101
110
1/64 bus clock.
#110
111
1/128 bus clock.
#111
FDSWW
Fault Detect Sample Window Width
9
3
read-write
000
Sample window width is 4 sample clock cycles.
#000
001
Sample window width is 8 sample clock cycles.
#001
010
Sample window width is 16 sample clock cycles.
#010
011
Sample window width is 32 sample clock cycles.
#011
100
Sample window width is 64 sample clock cycles.
#100
101
Sample window width is 128 sample clock cycles.
#101
110
Sample window width is 256 sample clock cycles.
#110
111
Sample window width is 512 sample clock cycles.
#111
FDSR
LCD Fault Detect Status Register
0xC
32
read-write
n
0x0
0x0
FDCF
Fault Detection Complete Flag
15
1
read-write
0
Fault detection is not completed.
#0
1
Fault detection is completed.
#1
FDCNT
Fault Detect Counter
0
8
read-only
00000000
No "one" samples.
#0
00000001
1 "one" samples.
#1
00000010
2 "one" samples.
#10
11111110
254 "one" samples.
#11111110
11111111
255 or more "one" samples. The FDCNT can overflow. Therefore, FDSWW and FDPRS must be reconfigured for proper sampling.
#11111111
GCR
LCD General Control Register
0x0
32
read-write
n
0x0
0x0
ALTDIV
LCD Alternate Clock Divider
12
2
read-write
00
Divide factor = 1 (No divide)
#00
01
Divide factor = 64
#01
10
Divide factor = 256
#10
11
Divide factor = 512
#11
ALTSOURCE
Selects the alternate clock source
11
1
read-write
0
Select Alternate Clock Source 1 (default)
#0
1
Select Alternate Clock Source 2
#1
CPSEL
Charge Pump or Resistor Bias Select
23
1
read-write
0
LCD charge pump is disabled. Resistor network selected. (The internal 1/3-bias is forced.)
#0
1
LCD charge pump is selected. Resistor network disabled. (The internal 1/3-bias is forced.)
#1
DUTY
LCD duty select
0
3
read-write
000
Use 1 BP (1/1 duty cycle).
#000
001
Use 2 BP (1/2 duty cycle).
#001
010
Use 3 BP (1/3 duty cycle).
#010
011
Use 4 BP (1/4 duty cycle). (Default)
#011
111
Use 8 BP (1/8 duty cycle).
#111
FDCIEN
LCD Fault Detection Complete Interrupt Enable
14
1
read-write
0
No interrupt request is generated by this event.
#0
1
When a fault is detected and FDCF bit is set, this event causes an interrupt request.
#1
FFR
Fast Frame Rate Select
10
1
read-write
0
Standard Frame Rate LCD Frame Freq: 23.3 (min) 73.1 (max)
#0
1
Fast Frame Rate (Standard Frame Rate *2) LCD Frame Freq: 46.6 (min) 146.2 (max)
#1
LADJ
Load Adjust
20
2
read-write
LCDDOZE
LCD Doze enable
9
1
read-write
0
Allows the LCD driver, charge pump, resistor bias network, and voltage regulator to continue running during Doze mode.
#0
1
Disables the LCD driver, charge pump, resistor bias network, and voltage regulator when MCU enters Doze mode.
#1
LCDEN
LCD Driver Enable
7
1
read-write
0
All front plane and back plane pins are disabled. The LCD controller system is also disabled, and all LCD waveform generation clocks are stopped. V LL3 is connected to V DD internally. All LCD pins, LCD_Pn, enabled using the LCD Pin Enable register, output a low value.
#0
1
LCD controller driver system is enabled, and front plane and back plane waveforms are generated. All LCD pins, LCD_Pn, enabled if PAD_SAFE is clearusing the LCD Pin Enable register, output an LCD driver waveform. The back plane pins output an LCD driver back plane waveform based on the settings of DUTY[2:0]. Charge pump or resistor bias is enabled.
#1
LCDSTP
LCD Stop
8
1
read-write
0
Allows the LCD driver, charge pump, resistor bias network, and voltage regulator to continue running during Stop mode.
#0
1
Disables the LCD driver, charge pump, resistor bias network, and voltage regulator when MCU enters Stop mode.
#1
LCLK
LCD Clock Prescaler
3
3
read-write
PADSAFE
Pad Safe State Enable
15
1
read-write
0
LCD frontplane and backplane functions enabled according to other LCD control bits
#0
1
LCD frontplane and backplane functions disabled
#1
RVEN
Regulated Voltage Enable
31
1
read-write
0
Regulated voltage disabled.
#0
1
Regulated voltage enabled.
#1
RVTRIM
Regulated Voltage Trim
24
4
read-write
SOURCE
LCD Clock Source Select
6
1
read-write
0
Selects the default clock as the LCD clock source.
#0
1
Selects output of the alternate clock source selection (see ALTSOURCE) as the LCD clock source.
#1
VSUPPLY
Voltage Supply Control
17
1
read-write
0
Drive VLL3 internally from VDD
#0
1
Drive VLL3 externally from VDD or drive VLL1 internally from vIREG
#1
PENH
LCD Pin Enable register
0x34
32
read-write
n
0x0
0x0
PEN
LCD Pin Enable
0
32
read-write
0
LCD operation disabled on LCD_Pn.
#0
1
LCD operation enabled on LCD_Pn.
#1
PENL
LCD Pin Enable register
0x20
32
read-write
n
0x0
0x0
PEN
LCD Pin Enable
0
32
read-write
0
LCD operation disabled on LCD_Pn.
#0
1
LCD operation enabled on LCD_Pn.
#1
WF0
LCD Waveform Register 0.
LCD
0x20
8
read-write
n
0x0
0x0
BPALCD0
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD0
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD0
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD0
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD0
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD0
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD0
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD0
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF1
LCD Waveform Register 1.
0x21
8
read-write
n
0x0
0x0
BPALCD1
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD1
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD1
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD1
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD1
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD1
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD1
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD1
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF10
LCD Waveform Register 10.
0x2A
8
read-write
n
0x0
0x0
BPALCD10
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD10
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD10
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD10
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD10
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD10
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD10
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD10
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF11
LCD Waveform Register 11.
0x2B
8
read-write
n
0x0
0x0
BPALCD11
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD11
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD11
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD11
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD11
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD11
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD11
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD11
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF11TO8
LCD Waveform register
LCD
0x28
32
read-write
n
0x0
0x0
WF10
Controls segments or phases connected to LCD_P10 as described above for WF3TO0[WF3].
16
8
read-write
WF11
Controls segments or phases connected to LCD_P11 as described above for WF3TO0[WF3].
24
8
read-write
WF8
Controls segments or phases connected to LCD_P8 as described above for WF3TO0[WF3].
0
8
read-write
WF9
Controls segments or phases connected to LCD_P9 as described above for WF3TO0[WF3].
8
8
read-write
WF12
LCD Waveform Register 12.
LCD
0x2C
8
read-write
n
0x0
0x0
BPALCD12
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD12
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD12
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD12
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD12
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD12
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD12
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD12
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF13
LCD Waveform Register 13.
0x2D
8
read-write
n
0x0
0x0
BPALCD13
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD13
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD13
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD13
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD13
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD13
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD13
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD13
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF14
LCD Waveform Register 14.
0x2E
8
read-write
n
0x0
0x0
BPALCD14
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD14
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD14
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD14
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD14
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD14
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD14
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD14
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF15
LCD Waveform Register 15.
0x2F
8
read-write
n
0x0
0x0
BPALCD15
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD15
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD15
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD15
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD15
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD15
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD15
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD15
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF15TO12
LCD Waveform register
LCD
0x2C
32
read-write
n
0x0
0x0
WF12
Controls segments or phases connected to LCD_P12 as described above for WF3TO0[WF3].
0
8
read-write
WF13
Controls segments or phases connected to LCD_P13 as described above for WF3TO0[WF3].
8
8
read-write
WF14
Controls segments or phases connected to LCD_P14 as described above for WF3TO0[WF3].
16
8
read-write
WF15
Controls segments or phases connected to LCD_P15 as described above for WF3TO0[WF3].
24
8
read-write
WF16
LCD Waveform Register 16.
LCD
0x30
8
read-write
n
0x0
0x0
BPALCD16
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD16
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD16
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD16
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD16
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD16
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD16
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD16
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF17
LCD Waveform Register 17.
0x31
8
read-write
n
0x0
0x0
BPALCD17
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD17
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD17
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD17
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD17
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD17
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD17
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD17
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF18
LCD Waveform Register 18.
0x32
8
read-write
n
0x0
0x0
BPALCD18
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD18
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD18
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD18
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD18
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD18
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD18
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD18
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF19
LCD Waveform Register 19.
0x33
8
read-write
n
0x0
0x0
BPALCD19
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD19
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD19
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD19
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD19
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD19
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD19
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD19
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF19TO16
LCD Waveform register
LCD
0x30
32
read-write
n
0x0
0x0
WF16
Controls segments or phases connected to LCD_P16 as described above for WF3TO0[WF3].
0
8
read-write
WF17
Controls segments or phases connected to LCD_P17 as described above for WF3TO0[WF3].
8
8
read-write
WF18
Controls segments or phases connected to LCD_P18 as described above for WF3TO0[WF3].
16
8
read-write
WF19
Controls segments or phases connected to LCD_P19 as described above for WF3TO0[WF3].
24
8
read-write
WF2
LCD Waveform Register 2.
0x22
8
read-write
n
0x0
0x0
BPALCD2
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD2
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD2
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD2
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD2
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD2
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD2
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD2
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF20
LCD Waveform Register 20.
LCD
0x34
8
read-write
n
0x0
0x0
BPALCD20
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD20
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD20
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD20
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD20
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD20
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD20
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD20
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF21
LCD Waveform Register 21.
0x35
8
read-write
n
0x0
0x0
BPALCD21
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD21
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD21
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD21
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD21
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD21
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD21
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD21
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF22
LCD Waveform Register 22.
0x36
8
read-write
n
0x0
0x0
BPALCD22
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD22
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD22
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD22
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD22
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD22
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD22
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD22
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF23
LCD Waveform Register 23.
0x37
8
read-write
n
0x0
0x0
BPALCD23
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD23
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD23
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD23
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD23
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD23
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD23
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD23
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF23TO20
LCD Waveform register
LCD
0x34
32
read-write
n
0x0
0x0
WF20
Controls segments or phases connected to LCD_P20 as described above for WF3TO0[WF3].
0
8
read-write
WF21
Controls segments or phases connected to LCD_P21 as described above for WF3TO0[WF3].
8
8
read-write
WF22
Controls segments or phases connected to LCD_P22 as described above for WF3TO0[WF3].
16
8
read-write
WF23
Controls segments or phases connected to LCD_P23 as described above for WF3TO0[WF3].
24
8
read-write
WF24
LCD Waveform Register 24.
LCD
0x38
8
read-write
n
0x0
0x0
BPALCD24
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD24
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD24
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD24
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD24
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD24
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD24
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD24
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF25
LCD Waveform Register 25.
0x39
8
read-write
n
0x0
0x0
BPALCD25
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD25
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD25
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD25
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD25
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD25
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD25
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD25
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF26
LCD Waveform Register 26.
0x3A
8
read-write
n
0x0
0x0
BPALCD26
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD26
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD26
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD26
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD26
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD26
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD26
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD26
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF27
LCD Waveform Register 27.
0x3B
8
read-write
n
0x0
0x0
BPALCD27
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD27
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD27
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD27
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD27
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD27
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD27
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD27
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF27TO24
LCD Waveform register
LCD
0x38
32
read-write
n
0x0
0x0
WF24
Controls segments or phases connected to LCD_P24 as described above for WF3TO0[WF3].
0
8
read-write
WF25
Controls segments or phases connected to LCD_P25 as described above for WF3TO0[WF3].
8
8
read-write
WF26
Controls segments or phases connected to LCD_P26 as described above for WF3TO0[WF3].
16
8
read-write
WF27
Controls segments or phases connected to LCD_P27 as described above for WF3TO0[WF3].
24
8
read-write
WF28
LCD Waveform Register 28.
LCD
0x3C
8
read-write
n
0x0
0x0
BPALCD28
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD28
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD28
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD28
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD28
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD28
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD28
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD28
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF29
LCD Waveform Register 29.
0x3D
8
read-write
n
0x0
0x0
BPALCD29
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD29
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD29
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD29
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD29
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD29
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD29
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD29
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF3
LCD Waveform Register 3.
0x23
8
read-write
n
0x0
0x0
BPALCD3
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD3
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD3
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD3
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD3
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD3
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD3
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD3
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF30
LCD Waveform Register 30.
0x3E
8
read-write
n
0x0
0x0
BPALCD30
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD30
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD30
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD30
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD30
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD30
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD30
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD30
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF31
LCD Waveform Register 31.
0x3F
8
read-write
n
0x0
0x0
BPALCD31
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD31
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD31
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD31
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD31
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD31
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD31
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD31
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF31TO28
LCD Waveform register
LCD
0x3C
32
read-write
n
0x0
0x0
WF28
Controls segments or phases connected to LCD_P28 as described above for WF3TO0[WF3].
0
8
read-write
WF29
Controls segments or phases connected to LCD_P29 as described above for WF3TO0[WF3].
8
8
read-write
WF30
Controls segments or phases connected to LCD_P30 as described above for WF3TO0[WF3].
16
8
read-write
WF31
Controls segments or phases connected to LCD_P31 as described above for WF3TO0[WF3].
24
8
read-write
WF32
LCD Waveform Register 32.
LCD
0x40
8
read-write
n
0x0
0x0
BPALCD32
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD32
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD32
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD32
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD32
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD32
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD32
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD32
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF33
LCD Waveform Register 33.
0x41
8
read-write
n
0x0
0x0
BPALCD33
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD33
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD33
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD33
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD33
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD33
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD33
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD33
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF34
LCD Waveform Register 34.
0x42
8
read-write
n
0x0
0x0
BPALCD34
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD34
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD34
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD34
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD34
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD34
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD34
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD34
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF35
LCD Waveform Register 35.
0x43
8
read-write
n
0x0
0x0
BPALCD35
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD35
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD35
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD35
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD35
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD35
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD35
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD35
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF35TO32
LCD Waveform register
LCD
0x40
32
read-write
n
0x0
0x0
WF32
Controls segments or phases connected to LCD_P32 as described above for WF3TO0[WF3].
0
8
read-write
WF33
Controls segments or phases connected to LCD_P33 as described above for WF3TO0[WF3].
8
8
read-write
WF34
Controls segments or phases connected to LCD_P34 as described above for WF3TO0[WF3].
16
8
read-write
WF35
Controls segments or phases connected to LCD_P35 as described above for WF3TO0[WF3].
24
8
read-write
WF36
LCD Waveform Register 36.
LCD
0x44
8
read-write
n
0x0
0x0
BPALCD36
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD36
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD36
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD36
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD36
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD36
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD36
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD36
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF37
LCD Waveform Register 37.
0x45
8
read-write
n
0x0
0x0
BPALCD37
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD37
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD37
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD37
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD37
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD37
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD37
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD37
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF38
LCD Waveform Register 38.
0x46
8
read-write
n
0x0
0x0
BPALCD38
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD38
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD38
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD38
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD38
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD38
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD38
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD38
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF39
LCD Waveform Register 39.
0x47
8
read-write
n
0x0
0x0
BPALCD39
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD39
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD39
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD39
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD39
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD39
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD39
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD39
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF39TO36
LCD Waveform register
LCD
0x44
32
read-write
n
0x0
0x0
WF36
Controls segments or phases connected to LCD_P36 as described above for WF3TO0[WF3].
0
8
read-write
WF37
Controls segments or phases connected to LCD_P37 as described above for WF3TO0[WF3].
8
8
read-write
WF38
Controls segments or phases connected to LCD_P38 as described above for WF3TO0[WF3].
16
8
read-write
WF39
Controls segments or phases connected to LCD_P39 as described above for WF3TO0[WF3].
24
8
read-write
WF3TO0
LCD Waveform register
LCD
0x20
32
read-write
n
0x0
0x0
WF0
Controls segments or phases connected to LCD_P0 as described above for WF3.
0
8
read-write
WF1
Controls segments or phases connected to LCD_P1 as described above for WF3.
8
8
read-write
WF2
Controls segments or phases connected to LCD_P2 as described above for WF3.
16
8
read-write
WF3
Segment-on front plane operation - Each bit turns on or off the segments associated with LCD_P3 in the following pattern: HGFEDCBA (most significant bit controls segment H and least significant bit controls segment A)
24
8
read-write
WF4
LCD Waveform Register 4.
LCD
0x24
8
read-write
n
0x0
0x0
BPALCD4
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD4
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD4
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD4
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD4
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD4
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD4
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD4
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF40
LCD Waveform Register 40.
LCD
0x48
8
read-write
n
0x0
0x0
BPALCD40
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD40
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD40
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD40
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD40
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD40
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD40
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD40
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF41
LCD Waveform Register 41.
0x49
8
read-write
n
0x0
0x0
BPALCD41
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD41
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD41
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD41
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD41
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD41
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD41
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD41
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF42
LCD Waveform Register 42.
0x4A
8
read-write
n
0x0
0x0
BPALCD42
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD42
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD42
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD42
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD42
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD42
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD42
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD42
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF43
LCD Waveform Register 43.
0x4B
8
read-write
n
0x0
0x0
BPALCD43
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD43
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD43
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD43
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD43
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD43
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD43
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD43
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF43TO40
LCD Waveform register
LCD
0x48
32
read-write
n
0x0
0x0
WF40
Controls segments or phases connected to LCD_P40 as described above for WF3TO0[WF3].
0
8
read-write
WF41
Controls segments or phases connected to LCD_P41 as described above for WF3TO0[WF3].
8
8
read-write
WF42
Controls segments or phases connected to LCD_P42 as described above for WF3TO0[WF3].
16
8
read-write
WF43
Controls segments or phases connected to LCD_P43 as described above for WF3TO0[WF3].
24
8
read-write
WF44
LCD Waveform Register 44.
LCD
0x4C
8
read-write
n
0x0
0x0
BPALCD44
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD44
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD44
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD44
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD44
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD44
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD44
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD44
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF45
LCD Waveform Register 45.
0x4D
8
read-write
n
0x0
0x0
BPALCD45
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD45
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD45
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD45
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD45
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD45
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD45
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD45
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF46
LCD Waveform Register 46.
0x4E
8
read-write
n
0x0
0x0
BPALCD46
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD46
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD46
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD46
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD46
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD46
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD46
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD46
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF47
LCD Waveform Register 47.
0x4F
8
read-write
n
0x0
0x0
BPALCD47
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD47
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD47
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD47
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD47
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD47
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD47
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD47
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF47TO44
LCD Waveform register
LCD
0x4C
32
read-write
n
0x0
0x0
WF44
Controls segments or phases connected to LCD_P44 as described above for WF3TO0[WF3].
0
8
read-write
WF45
Controls segments or phases connected to LCD_P45 as described above for WF3TO0[WF3].
8
8
read-write
WF46
Controls segments or phases connected to LCD_P46 as described above for WF3TO0[WF3].
16
8
read-write
WF47
Controls segments or phases connected to LCD_P47 as described above for WF3TO0[WF3].
24
8
read-write
WF48
LCD Waveform Register 48.
LCD
0x50
8
read-write
n
0x0
0x0
BPALCD48
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD48
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD48
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD48
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD48
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD48
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD48
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD48
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF49
LCD Waveform Register 49.
0x51
8
read-write
n
0x0
0x0
BPALCD49
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD49
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD49
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD49
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD49
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD49
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD49
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD49
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF5
LCD Waveform Register 5.
0x25
8
read-write
n
0x0
0x0
BPALCD5
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD5
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD5
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD5
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD5
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD5
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD5
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD5
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF50
LCD Waveform Register 50.
0x52
8
read-write
n
0x0
0x0
BPALCD50
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD50
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD50
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD50
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD50
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD50
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD50
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD50
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF51
LCD Waveform Register 51.
0x53
8
read-write
n
0x0
0x0
BPALCD51
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD51
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD51
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD51
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD51
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD51
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD51
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD51
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF51TO48
LCD Waveform register
LCD
0x50
32
read-write
n
0x0
0x0
WF48
Controls segments or phases connected to LCD_P48 as described above for WF3TO0[WF3].
0
8
read-write
WF49
Controls segments or phases connected to LCD_P49 as described above for WF3TO0[WF3].
8
8
read-write
WF50
Controls segments or phases connected to LCD_P50 as described above for WF3TO0[WF3].
16
8
read-write
WF51
Controls segments or phases connected to LCD_P51 as described above for WF3TO0[WF3].
24
8
read-write
WF52
LCD Waveform Register 52.
LCD
0x54
8
read-write
n
0x0
0x0
BPALCD52
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD52
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD52
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD52
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD52
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD52
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD52
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD52
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF53
LCD Waveform Register 53.
0x55
8
read-write
n
0x0
0x0
BPALCD53
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD53
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD53
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD53
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD53
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD53
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD53
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD53
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF54
LCD Waveform Register 54.
0x56
8
read-write
n
0x0
0x0
BPALCD54
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD54
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD54
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD54
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD54
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD54
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD54
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD54
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF55
LCD Waveform Register 55.
0x57
8
read-write
n
0x0
0x0
BPALCD55
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD55
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD55
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD55
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD55
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD55
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD55
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD55
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF55TO52
LCD Waveform register
LCD
0x54
32
read-write
n
0x0
0x0
WF52
Controls segments or phases connected to LCD_P52 as described above for WF3TO0[WF3].
0
8
read-write
WF53
Controls segments or phases connected to LCD_P53 as described above for WF3TO0[WF3].
8
8
read-write
WF54
Controls segments or phases connected to LCD_P54 as described above for WF3TO0[WF3].
16
8
read-write
WF55
Controls segments or phases connected to LCD_P55 as described above for WF3TO0[WF3].
24
8
read-write
WF56
LCD Waveform Register 56.
LCD
0x58
8
read-write
n
0x0
0x0
BPALCD56
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD56
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD56
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD56
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD56
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD56
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD56
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD56
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF57
LCD Waveform Register 57.
0x59
8
read-write
n
0x0
0x0
BPALCD57
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD57
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD57
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD57
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD57
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD57
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD57
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD57
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF58
LCD Waveform Register 58.
0x5A
8
read-write
n
0x0
0x0
BPALCD58
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD58
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD58
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD58
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD58
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD58
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD58
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD58
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF59
LCD Waveform Register 59.
0x5B
8
read-write
n
0x0
0x0
BPALCD59
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD59
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD59
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD59
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD59
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD59
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD59
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD59
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF59TO56
LCD Waveform register
LCD
0x58
32
read-write
n
0x0
0x0
WF56
Controls segments or phases connected to LCD_P56 as described above for WF3TO0[WF3].
0
8
read-write
WF57
Controls segments or phases connected to LCD_P57 as described above for WF3TO0[WF3].
8
8
read-write
WF58
Controls segments or phases connected to LCD_P58 as described above for WF3TO0[WF3].
16
8
read-write
WF59
Controls segments or phases connected to LCD_P59 as described above for WF3TO0[WF3].
24
8
read-write
WF6
LCD Waveform Register 6.
0x26
8
read-write
n
0x0
0x0
BPALCD6
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD6
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD6
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD6
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD6
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD6
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD6
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD6
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF60
LCD Waveform Register 60.
LCD
0x5C
8
read-write
n
0x0
0x0
BPALCD60
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD60
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD60
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD60
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD60
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD60
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD60
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD60
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF61
LCD Waveform Register 61.
0x5D
8
read-write
n
0x0
0x0
BPALCD61
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD61
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD61
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD61
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD61
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD61
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD61
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD61
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF62
LCD Waveform Register 62.
0x5E
8
read-write
n
0x0
0x0
BPALCD62
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD62
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD62
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD62
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD62
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD62
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD62
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD62
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF63
LCD Waveform Register 63.
0x5F
8
read-write
n
0x0
0x0
BPALCD63
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD63
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD63
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD63
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD63
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD63
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD63
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD63
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF63TO60
LCD Waveform register
LCD
0x5C
32
read-write
n
0x0
0x0
WF60
Controls segments or phases connected to LCD_P60 as described above for WF3TO0[WF3].
0
8
read-write
WF61
Controls segments or phases connected to LCD_P61 as described above for WF3TO0[WF3].
8
8
read-write
WF62
Controls segments or phases connected to LCD_P62 as described above for WF3TO0[WF3].
16
8
read-write
WF63
Controls segments or phases connected to LCD_P63 as described above for WF3TO0[WF3].
24
8
read-write
WF7
LCD Waveform Register 7.
0x27
8
read-write
n
0x0
0x0
BPALCD7
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD7
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD7
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD7
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD7
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD7
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD7
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD7
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF7TO4
LCD Waveform register
LCD
0x24
32
read-write
n
0x0
0x0
WF4
Controls segments or phases connected to LCD_P4 as described above for WF3TO0[WF3].
0
8
read-write
WF5
Controls segments or phases connected to LCD_P5 as described above for WF3TO0[WF3].
8
8
read-write
WF6
Controls segments or phases connected to LCD_P6 as described above for WF3TO0[WF3].
16
8
read-write
WF7
Controls segments or phases connected to LCD_P7 as described above for WF3TO0[WF3].
24
8
read-write
WF8
LCD Waveform Register 8.
LCD
0x28
8
read-write
n
0x0
0x0
BPALCD8
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD8
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD8
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD8
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD8
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD8
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD8
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD8
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF9
LCD Waveform Register 9.
0x29
8
read-write
n
0x0
0x0
BPALCD9
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD9
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD9
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD9
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD9
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD9
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD9
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD9
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
LLWU
Low leakage wakeup unit
LLWU
0x0
0x0
0xA
registers
n
LLWU
7
F1
LLWU Flag 1 register
0x5
8
read-write
n
0x0
0x0
WUF0
Wakeup Flag For LLWU_P0
0
1
read-write
0
LLWU_P0 input was not a wakeup source
#0
1
LLWU_P0 input was a wakeup source
#1
WUF1
Wakeup Flag For LLWU_P1
1
1
read-write
0
LLWU_P1 input was not a wakeup source
#0
1
LLWU_P1 input was a wakeup source
#1
WUF2
Wakeup Flag For LLWU_P2
2
1
read-write
0
LLWU_P2 input was not a wakeup source
#0
1
LLWU_P2 input was a wakeup source
#1
WUF3
Wakeup Flag For LLWU_P3
3
1
read-write
0
LLWU_P3 input was not a wake-up source
#0
1
LLWU_P3 input was a wake-up source
#1
WUF4
Wakeup Flag For LLWU_P4
4
1
read-write
0
LLWU_P4 input was not a wakeup source
#0
1
LLWU_P4 input was a wakeup source
#1
WUF5
Wakeup Flag For LLWU_P5
5
1
read-write
0
LLWU_P5 input was not a wakeup source
#0
1
LLWU_P5 input was a wakeup source
#1
WUF6
Wakeup Flag For LLWU_P6
6
1
read-write
0
LLWU_P6 input was not a wakeup source
#0
1
LLWU_P6 input was a wakeup source
#1
WUF7
Wakeup Flag For LLWU_P7
7
1
read-write
0
LLWU_P7 input was not a wakeup source
#0
1
LLWU_P7 input was a wakeup source
#1
F2
LLWU Flag 2 register
0x6
8
read-write
n
0x0
0x0
WUF10
Wakeup Flag For LLWU_P10
2
1
read-write
0
LLWU_P10 input was not a wakeup source
#0
1
LLWU_P10 input was a wakeup source
#1
WUF11
Wakeup Flag For LLWU_P11
3
1
read-write
0
LLWU_P11 input was not a wakeup source
#0
1
LLWU_P11 input was a wakeup source
#1
WUF12
Wakeup Flag For LLWU_P12
4
1
read-write
0
LLWU_P12 input was not a wakeup source
#0
1
LLWU_P12 input was a wakeup source
#1
WUF13
Wakeup Flag For LLWU_P13
5
1
read-write
0
LLWU_P13 input was not a wakeup source
#0
1
LLWU_P13 input was a wakeup source
#1
WUF14
Wakeup Flag For LLWU_P14
6
1
read-write
0
LLWU_P14 input was not a wakeup source
#0
1
LLWU_P14 input was a wakeup source
#1
WUF15
Wakeup Flag For LLWU_P15
7
1
read-write
0
LLWU_P15 input was not a wakeup source
#0
1
LLWU_P15 input was a wakeup source
#1
WUF8
Wakeup Flag For LLWU_P8
0
1
read-write
0
LLWU_P8 input was not a wakeup source
#0
1
LLWU_P8 input was a wakeup source
#1
WUF9
Wakeup Flag For LLWU_P9
1
1
read-write
0
LLWU_P9 input was not a wakeup source
#0
1
LLWU_P9 input was a wakeup source
#1
F3
LLWU Flag 3 register
0x7
8
read-only
n
0x0
0x0
MWUF0
Wakeup flag For module 0
0
1
read-only
0
Module 0 input was not a wakeup source
#0
1
Module 0 input was a wakeup source
#1
MWUF1
Wakeup flag For module 1
1
1
read-only
0
Module 1 input was not a wakeup source
#0
1
Module 1 input was a wakeup source
#1
MWUF2
Wakeup flag For module 2
2
1
read-only
0
Module 2 input was not a wakeup source
#0
1
Module 2 input was a wakeup source
#1
MWUF3
Wakeup flag For module 3
3
1
read-only
0
Module 3 input was not a wakeup source
#0
1
Module 3 input was a wakeup source
#1
MWUF4
Wakeup flag For module 4
4
1
read-only
0
Module 4 input was not a wakeup source
#0
1
Module 4 input was a wakeup source
#1
MWUF5
Wakeup flag For module 5
5
1
read-only
0
Module 5 input was not a wakeup source
#0
1
Module 5 input was a wakeup source
#1
MWUF6
Wakeup flag For module 6
6
1
read-only
0
Module 6 input was not a wakeup source
#0
1
Module 6 input was a wakeup source
#1
MWUF7
Wakeup flag For module 7
7
1
read-only
0
Module 7 input was not a wakeup source
#0
1
Module 7 input was a wakeup source
#1
FILT1
LLWU Pin Filter 1 register
0x8
8
read-write
n
0x0
0x0
FILTE
Digital Filter On External Pin
5
2
read-write
00
Filter disabled
#00
01
Filter posedge detect enabled
#01
10
Filter negedge detect enabled
#10
11
Filter any edge detect enabled
#11
FILTF
Filter Detect Flag
7
1
read-write
0
Pin Filter 1 was not a wakeup source
#0
1
Pin Filter 1 was a wakeup source
#1
FILTSEL
Filter Pin Select
0
4
read-write
0000
Select LLWU_P0 for filter
#0000
1111
Select LLWU_P15 for filter
#1111
FILT2
LLWU Pin Filter 2 register
0x9
8
read-write
n
0x0
0x0
FILTE
Digital Filter On External Pin
5
2
read-write
00
Filter disabled
#00
01
Filter posedge detect enabled
#01
10
Filter negedge detect enabled
#10
11
Filter any edge detect enabled
#11
FILTF
Filter Detect Flag
7
1
read-write
0
Pin Filter 2 was not a wakeup source
#0
1
Pin Filter 2 was a wakeup source
#1
FILTSEL
Filter Pin Select
0
4
read-write
0000
Select LLWU_P0 for filter
#0000
1111
Select LLWU_P15 for filter
#1111
ME
LLWU Module Enable register
0x4
8
read-write
n
0x0
0x0
WUME0
Wakeup Module Enable For Module 0
0
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME1
Wakeup Module Enable for Module 1
1
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME2
Wakeup Module Enable For Module 2
2
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME3
Wakeup Module Enable For Module 3
3
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME4
Wakeup Module Enable For Module 4
4
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME5
Wakeup Module Enable For Module 5
5
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME6
Wakeup Module Enable For Module 6
6
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME7
Wakeup Module Enable For Module 7
7
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
PE1
LLWU Pin Enable 1 register
0x0
8
read-write
n
0x0
0x0
WUPE0
Wakeup Pin Enable For LLWU_P0
0
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE1
Wakeup Pin Enable For LLWU_P1
2
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE2
Wakeup Pin Enable For LLWU_P2
4
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE3
Wakeup Pin Enable For LLWU_P3
6
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
PE2
LLWU Pin Enable 2 register
0x1
8
read-write
n
0x0
0x0
WUPE4
Wakeup Pin Enable For LLWU_P4
0
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE5
Wakeup Pin Enable For LLWU_P5
2
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE6
Wakeup Pin Enable For LLWU_P6
4
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE7
Wakeup Pin Enable For LLWU_P7
6
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
PE3
LLWU Pin Enable 3 register
0x2
8
read-write
n
0x0
0x0
WUPE10
Wakeup Pin Enable For LLWU_P10
4
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE11
Wakeup Pin Enable For LLWU_P11
6
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE8
Wakeup Pin Enable For LLWU_P8
0
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE9
Wakeup Pin Enable For LLWU_P9
2
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
PE4
LLWU Pin Enable 4 register
0x3
8
read-write
n
0x0
0x0
WUPE12
Wakeup Pin Enable For LLWU_P12
0
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE13
Wakeup Pin Enable For LLWU_P13
2
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE14
Wakeup Pin Enable For LLWU_P14
4
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE15
Wakeup Pin Enable For LLWU_P15
6
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
LPTMR0
Low Power Timer
LPTMR0
0x0
0x0
0x10
registers
n
LPTMR0
28
CMR
Low Power Timer Compare Register
0x8
32
read-write
n
0x0
0x0
COMPARE
Compare Value
0
16
read-write
CNR
Low Power Timer Counter Register
0xC
32
read-write
n
0x0
0x0
COUNTER
Counter Value
0
16
read-write
CSR
Low Power Timer Control Status Register
0x0
32
read-write
n
0x0
0x0
TCF
Timer Compare Flag
7
1
read-write
0
The value of CNR is not equal to CMR and increments.
#0
1
The value of CNR is equal to CMR and increments.
#1
TEN
Timer Enable
0
1
read-write
0
LPTMR is disabled and internal logic is reset.
#0
1
LPTMR is enabled.
#1
TFC
Timer Free-Running Counter
2
1
read-write
0
CNR is reset whenever TCF is set.
#0
1
CNR is reset on overflow.
#1
TIE
Timer Interrupt Enable
6
1
read-write
0
Timer interrupt disabled.
#0
1
Timer interrupt enabled.
#1
TMS
Timer Mode Select
1
1
read-write
0
Time Counter mode.
#0
1
Pulse Counter mode.
#1
TPP
Timer Pin Polarity
3
1
read-write
0
Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
#0
1
Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
#1
TPS
Timer Pin Select
4
2
read-write
00
Pulse counter input 0 is selected.
#00
01
Pulse counter input 1 is selected.
#01
10
Pulse counter input 2 is selected.
#10
11
Pulse counter input 3 is selected.
#11
PSR
Low Power Timer Prescale Register
0x4
32
read-write
n
0x0
0x0
PBYP
Prescaler Bypass
2
1
read-write
0
Prescaler/glitch filter is enabled.
#0
1
Prescaler/glitch filter is bypassed.
#1
PCS
Prescaler Clock Select
0
2
read-write
00
Prescaler/glitch filter clock 0 selected.
#00
01
Prescaler/glitch filter clock 1 selected.
#01
10
Prescaler/glitch filter clock 2 selected.
#10
11
Prescaler/glitch filter clock 3 selected.
#11
PRESCALE
Prescale Value
3
4
read-write
0000
Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.
#0000
0001
Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.
#0001
0010
Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.
#0010
0011
Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.
#0011
0100
Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.
#0100
0101
Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.
#0101
0110
Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.
#0110
0111
Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.
#0111
1000
Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.
#1000
1001
Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.
#1001
1010
Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.
#1010
1011
Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.
#1011
1100
Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.
#1100
1101
Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.
#1101
1110
Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.
#1110
1111
Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.
#1111
LPUART0
Universal Asynchronous Receiver/Transmitter
LPUART
0x0
0x0
0x14
registers
n
LPUART0
12
BAUD
LPUART Baud Rate Register
0x0
32
read-write
n
0x0
0x0
BOTHEDGE
Both Edge Sampling
17
1
read-write
0
Receiver samples input data using the rising edge of the baud rate clock.
#0
1
Receiver samples input data using the rising and falling edge of the baud rate clock.
#1
LBKDIE
LIN Break Detect Interrupt Enable
15
1
read-write
0
Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).
#0
1
Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.
#1
M10
10-bit Mode select
29
1
read-write
0
Receiver and transmitter use 8-bit or 9-bit data characters.
#0
1
Receiver and transmitter use 10-bit data characters.
#1
MAEN1
Match Address Mode Enable 1
31
1
read-write
0
Normal operation.
#0
1
Enables automatic address matching or data matching mode for MATCH[MA1].
#1
MAEN2
Match Address Mode Enable 2
30
1
read-write
0
Normal operation.
#0
1
Enables automatic address matching or data matching mode for MATCH[MA2].
#1
MATCFG
Match Configuration
18
2
read-write
00
Address Match Wakeup
#00
01
Idle Match Wakeup
#01
10
Match On and Match Off
#10
11
Enables RWU on Data Match and Match On/Off
#11
OSR
Oversampling Ratio
24
5
read-write
RDMAE
Receiver Full DMA Enable
21
1
read-write
0
DMA request disabled.
#0
1
DMA request enabled.
#1
RESYNCDIS
Resynchronization Disable
16
1
read-write
0
Resynchronization during received data word is supported
#0
1
Resynchronization during received data word is disabled
#1
RXEDGIE
RX Input Active Edge Interrupt Enable
14
1
read-write
0
Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).
#0
1
Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.
#1
SBNS
Stop Bit Number Select
13
1
read-write
0
One stop bit.
#0
1
Two stop bits.
#1
SBR
Baud Rate Modulo Divisor.
0
13
read-write
TDMAE
Transmitter DMA Enable
23
1
read-write
0
DMA request disabled.
#0
1
DMA request enabled.
#1
CTRL
LPUART Control Register
0x8
32
read-write
n
0x0
0x0
DOZEEN
Doze Enable
6
1
read-write
0
LPUART is enabled in Doze mode.
#0
1
LPUART is disabled in Doze mode.
#1
FEIE
Framing Error Interrupt Enable
25
1
read-write
0
FE interrupts disabled; use polling.
#0
1
Hardware interrupt requested when FE is set.
#1
IDLECFG
Idle Configuration
8
3
read-write
000
1 idle character
#000
001
2 idle characters
#001
010
4 idle characters
#010
011
8 idle characters
#011
100
16 idle characters
#100
101
32 idle characters
#101
110
64 idle characters
#110
111
128 idle characters
#111
ILIE
Idle Line Interrupt Enable
20
1
read-write
0
Hardware interrupts from IDLE disabled; use polling.
#0
1
Hardware interrupt requested when IDLE flag is 1.
#1
ILT
Idle Line Type Select
2
1
read-write
0
Idle character bit count starts after start bit.
#0
1
Idle character bit count starts after stop bit.
#1
LOOPS
Loop Mode Select
7
1
read-write
0
Normal operation - LPUART_RX and LPUART_TX use separate pins.
#0
1
Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
#1
M
9-Bit or 8-Bit Mode Select
4
1
read-write
0
Receiver and transmitter use 8-bit data characters.
#0
1
Receiver and transmitter use 9-bit data characters.
#1
MA1IE
Match 1 Interrupt Enable
15
1
read-write
0
MA1F interrupt disabled
#0
1
MA1F interrupt enabled
#1
MA2IE
Match 2 Interrupt Enable
14
1
read-write
0
MA2F interrupt disabled
#0
1
MA2F interrupt enabled
#1
NEIE
Noise Error Interrupt Enable
26
1
read-write
0
NF interrupts disabled; use polling.
#0
1
Hardware interrupt requested when NF is set.
#1
ORIE
Overrun Interrupt Enable
27
1
read-write
0
OR interrupts disabled; use polling.
#0
1
Hardware interrupt requested when OR is set.
#1
PE
Parity Enable
1
1
read-write
0
No hardware parity generation or checking.
#0
1
Parity enabled.
#1
PEIE
Parity Error Interrupt Enable
24
1
read-write
0
PF interrupts disabled; use polling).
#0
1
Hardware interrupt requested when PF is set.
#1
PT
Parity Type
0
1
read-write
0
Even parity.
#0
1
Odd parity.
#1
R8T9
Receive Bit 8 / Transmit Bit 9
31
1
read-write
R9T8
Receive Bit 9 / Transmit Bit 8
30
1
read-write
RE
Receiver Enable
18
1
read-write
0
Receiver disabled.
#0
1
Receiver enabled.
#1
RIE
Receiver Interrupt Enable
21
1
read-write
0
Hardware interrupts from RDRF disabled; use polling.
#0
1
Hardware interrupt requested when RDRF flag is 1.
#1
RSRC
Receiver Source Select
5
1
read-write
0
Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin.
#0
1
Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input.
#1
RWU
Receiver Wakeup Control
17
1
read-write
0
Normal receiver operation.
#0
1
LPUART receiver in standby waiting for wakeup condition.
#1
SBK
Send Break
16
1
read-write
0
Normal transmitter operation.
#0
1
Queue break character(s) to be sent.
#1
TCIE
Transmission Complete Interrupt Enable for
22
1
read-write
0
Hardware interrupts from TC disabled; use polling.
#0
1
Hardware interrupt requested when TC flag is 1.
#1
TE
Transmitter Enable
19
1
read-write
0
Transmitter disabled.
#0
1
Transmitter enabled.
#1
TIE
Transmit Interrupt Enable
23
1
read-write
0
Hardware interrupts from TDRE disabled; use polling.
#0
1
Hardware interrupt requested when TDRE flag is 1.
#1
TXDIR
LPUART_TX Pin Direction in Single-Wire Mode
29
1
read-write
0
LPUART_TX pin is an input in single-wire mode.
#0
1
LPUART_TX pin is an output in single-wire mode.
#1
TXINV
Transmit Data Inversion
28
1
read-write
0
Transmit data not inverted.
#0
1
Transmit data inverted.
#1
WAKE
Receiver Wakeup Method Select
3
1
read-write
0
Configures RWU for idle-line wakeup.
#0
1
Configures RWU with address-mark wakeup.
#1
DATA
LPUART Data Register
0xC
32
read-write
n
0x0
0x0
FRETSC
Frame Error / Transmit Special Character
13
1
read-write
0
The dataword was received without a frame error on read, transmit a normal character on write.
#0
1
The dataword was received with a frame error, transmit an idle or break character on transmit.
#1
IDLINE
Idle Line
11
1
read-only
0
Receiver was not idle before receiving this character.
#0
1
Receiver was idle before receiving this character.
#1
NOISY
The current received dataword contained in DATA[R9:R0] was received with noise.
15
1
read-only
0
The dataword was received without noise.
#0
1
The data was received with noise.
#1
PARITYE
The current received dataword contained in DATA[R9:R0] was received with a parity error.
14
1
read-only
0
The dataword was received without a parity error.
#0
1
The dataword was received with a parity error.
#1
R0T0
Read receive data buffer 0 or write transmit data buffer 0.
0
1
read-write
R1T1
Read receive data buffer 1 or write transmit data buffer 1.
1
1
read-write
R2T2
Read receive data buffer 2 or write transmit data buffer 2.
2
1
read-write
R3T3
Read receive data buffer 3 or write transmit data buffer 3.
3
1
read-write
R4T4
Read receive data buffer 4 or write transmit data buffer 4.
4
1
read-write
R5T5
Read receive data buffer 5 or write transmit data buffer 5.
5
1
read-write
R6T6
Read receive data buffer 6 or write transmit data buffer 6.
6
1
read-write
R7T7
Read receive data buffer 7 or write transmit data buffer 7.
7
1
read-write
R8T8
Read receive data buffer 8 or write transmit data buffer 8.
8
1
read-write
R9T9
Read receive data buffer 9 or write transmit data buffer 9.
9
1
read-write
RXEMPT
Receive Buffer Empty
12
1
read-only
0
Receive buffer contains valid data.
#0
1
Receive buffer is empty, data returned on read is not valid.
#1
MATCH
LPUART Match Address Register
0x10
32
read-write
n
0x0
0x0
MA1
Match Address 1
0
10
read-write
MA2
Match Address 2
16
10
read-write
STAT
LPUART Status Register
0x4
32
read-write
n
0x0
0x0
BRK13
Break Character Generation Length
26
1
read-write
0
Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
#0
1
Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).
#1
FE
Framing Error Flag
17
1
read-write
0
No framing error detected. This does not guarantee the framing is correct.
#0
1
Framing error.
#1
IDLE
Idle Line Flag
20
1
read-write
0
No idle line detected.
#0
1
Idle line was detected.
#1
LBKDE
LIN Break Detection Enable
25
1
read-write
0
Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
#0
1
Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
#1
LBKDIF
LIN Break Detect Interrupt Flag
31
1
read-write
0
No LIN break character has been detected.
#0
1
LIN break character has been detected.
#1
MA1F
Match 1 Flag
15
1
read-write
0
Received data is not equal to MA1
#0
1
Received data is equal to MA1
#1
MA2F
Match 2 Flag
14
1
read-write
0
Received data is not equal to MA2
#0
1
Received data is equal to MA2
#1
MSBF
MSB First
29
1
read-write
0
LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
#0
1
MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
#1
NF
Noise Flag
18
1
read-write
0
No noise detected.
#0
1
Noise detected in the received character in LPUART_DATA.
#1
OR
Receiver Overrun Flag
19
1
read-write
0
No overrun.
#0
1
Receive overrun (new LPUART data lost).
#1
PF
Parity Error Flag
16
1
read-write
0
No parity error.
#0
1
Parity error.
#1
RAF
Receiver Active Flag
24
1
read-only
0
LPUART receiver idle waiting for a start bit.
#0
1
LPUART receiver active (LPUART_RX input not idle).
#1
RDRF
Receive Data Register Full Flag
21
1
read-only
0
Receive data buffer empty.
#0
1
Receive data buffer full.
#1
RWUID
Receive Wake Up Idle Detect
27
1
read-write
0
During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match.
#0
1
During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match.
#1
RXEDGIF
LPUART_RX Pin Active Edge Interrupt Flag
30
1
read-write
0
No active edge on the receive pin has occurred.
#0
1
An active edge on the receive pin has occurred.
#1
RXINV
Receive Data Inversion
28
1
read-write
0
Receive data not inverted.
#0
1
Receive data inverted.
#1
TC
Transmission Complete Flag
22
1
read-only
0
Transmitter active (sending data, a preamble, or a break).
#0
1
Transmitter idle (transmission activity complete).
#1
TDRE
Transmit Data Register Empty Flag
23
1
read-only
0
Transmit data buffer full.
#0
1
Transmit data buffer empty.
#1
LPUART1
Universal Asynchronous Receiver/Transmitter
LPUART
0x0
0x0
0x14
registers
n
LPUART1
13
BAUD
LPUART Baud Rate Register
0x0
32
read-write
n
0x0
0x0
BOTHEDGE
Both Edge Sampling
17
1
read-write
0
Receiver samples input data using the rising edge of the baud rate clock.
#0
1
Receiver samples input data using the rising and falling edge of the baud rate clock.
#1
LBKDIE
LIN Break Detect Interrupt Enable
15
1
read-write
0
Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).
#0
1
Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.
#1
M10
10-bit Mode select
29
1
read-write
0
Receiver and transmitter use 8-bit or 9-bit data characters.
#0
1
Receiver and transmitter use 10-bit data characters.
#1
MAEN1
Match Address Mode Enable 1
31
1
read-write
0
Normal operation.
#0
1
Enables automatic address matching or data matching mode for MATCH[MA1].
#1
MAEN2
Match Address Mode Enable 2
30
1
read-write
0
Normal operation.
#0
1
Enables automatic address matching or data matching mode for MATCH[MA2].
#1
MATCFG
Match Configuration
18
2
read-write
00
Address Match Wakeup
#00
01
Idle Match Wakeup
#01
10
Match On and Match Off
#10
11
Enables RWU on Data Match and Match On/Off
#11
OSR
Oversampling Ratio
24
5
read-write
RDMAE
Receiver Full DMA Enable
21
1
read-write
0
DMA request disabled.
#0
1
DMA request enabled.
#1
RESYNCDIS
Resynchronization Disable
16
1
read-write
0
Resynchronization during received data word is supported
#0
1
Resynchronization during received data word is disabled
#1
RXEDGIE
RX Input Active Edge Interrupt Enable
14
1
read-write
0
Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).
#0
1
Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.
#1
SBNS
Stop Bit Number Select
13
1
read-write
0
One stop bit.
#0
1
Two stop bits.
#1
SBR
Baud Rate Modulo Divisor.
0
13
read-write
TDMAE
Transmitter DMA Enable
23
1
read-write
0
DMA request disabled.
#0
1
DMA request enabled.
#1
CTRL
LPUART Control Register
0x8
32
read-write
n
0x0
0x0
DOZEEN
Doze Enable
6
1
read-write
0
LPUART is enabled in Doze mode.
#0
1
LPUART is disabled in Doze mode.
#1
FEIE
Framing Error Interrupt Enable
25
1
read-write
0
FE interrupts disabled; use polling.
#0
1
Hardware interrupt requested when FE is set.
#1
IDLECFG
Idle Configuration
8
3
read-write
000
1 idle character
#000
001
2 idle characters
#001
010
4 idle characters
#010
011
8 idle characters
#011
100
16 idle characters
#100
101
32 idle characters
#101
110
64 idle characters
#110
111
128 idle characters
#111
ILIE
Idle Line Interrupt Enable
20
1
read-write
0
Hardware interrupts from IDLE disabled; use polling.
#0
1
Hardware interrupt requested when IDLE flag is 1.
#1
ILT
Idle Line Type Select
2
1
read-write
0
Idle character bit count starts after start bit.
#0
1
Idle character bit count starts after stop bit.
#1
LOOPS
Loop Mode Select
7
1
read-write
0
Normal operation - LPUART_RX and LPUART_TX use separate pins.
#0
1
Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
#1
M
9-Bit or 8-Bit Mode Select
4
1
read-write
0
Receiver and transmitter use 8-bit data characters.
#0
1
Receiver and transmitter use 9-bit data characters.
#1
MA1IE
Match 1 Interrupt Enable
15
1
read-write
0
MA1F interrupt disabled
#0
1
MA1F interrupt enabled
#1
MA2IE
Match 2 Interrupt Enable
14
1
read-write
0
MA2F interrupt disabled
#0
1
MA2F interrupt enabled
#1
NEIE
Noise Error Interrupt Enable
26
1
read-write
0
NF interrupts disabled; use polling.
#0
1
Hardware interrupt requested when NF is set.
#1
ORIE
Overrun Interrupt Enable
27
1
read-write
0
OR interrupts disabled; use polling.
#0
1
Hardware interrupt requested when OR is set.
#1
PE
Parity Enable
1
1
read-write
0
No hardware parity generation or checking.
#0
1
Parity enabled.
#1
PEIE
Parity Error Interrupt Enable
24
1
read-write
0
PF interrupts disabled; use polling).
#0
1
Hardware interrupt requested when PF is set.
#1
PT
Parity Type
0
1
read-write
0
Even parity.
#0
1
Odd parity.
#1
R8T9
Receive Bit 8 / Transmit Bit 9
31
1
read-write
R9T8
Receive Bit 9 / Transmit Bit 8
30
1
read-write
RE
Receiver Enable
18
1
read-write
0
Receiver disabled.
#0
1
Receiver enabled.
#1
RIE
Receiver Interrupt Enable
21
1
read-write
0
Hardware interrupts from RDRF disabled; use polling.
#0
1
Hardware interrupt requested when RDRF flag is 1.
#1
RSRC
Receiver Source Select
5
1
read-write
0
Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin.
#0
1
Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input.
#1
RWU
Receiver Wakeup Control
17
1
read-write
0
Normal receiver operation.
#0
1
LPUART receiver in standby waiting for wakeup condition.
#1
SBK
Send Break
16
1
read-write
0
Normal transmitter operation.
#0
1
Queue break character(s) to be sent.
#1
TCIE
Transmission Complete Interrupt Enable for
22
1
read-write
0
Hardware interrupts from TC disabled; use polling.
#0
1
Hardware interrupt requested when TC flag is 1.
#1
TE
Transmitter Enable
19
1
read-write
0
Transmitter disabled.
#0
1
Transmitter enabled.
#1
TIE
Transmit Interrupt Enable
23
1
read-write
0
Hardware interrupts from TDRE disabled; use polling.
#0
1
Hardware interrupt requested when TDRE flag is 1.
#1
TXDIR
LPUART_TX Pin Direction in Single-Wire Mode
29
1
read-write
0
LPUART_TX pin is an input in single-wire mode.
#0
1
LPUART_TX pin is an output in single-wire mode.
#1
TXINV
Transmit Data Inversion
28
1
read-write
0
Transmit data not inverted.
#0
1
Transmit data inverted.
#1
WAKE
Receiver Wakeup Method Select
3
1
read-write
0
Configures RWU for idle-line wakeup.
#0
1
Configures RWU with address-mark wakeup.
#1
DATA
LPUART Data Register
0xC
32
read-write
n
0x0
0x0
FRETSC
Frame Error / Transmit Special Character
13
1
read-write
0
The dataword was received without a frame error on read, transmit a normal character on write.
#0
1
The dataword was received with a frame error, transmit an idle or break character on transmit.
#1
IDLINE
Idle Line
11
1
read-only
0
Receiver was not idle before receiving this character.
#0
1
Receiver was idle before receiving this character.
#1
NOISY
The current received dataword contained in DATA[R9:R0] was received with noise.
15
1
read-only
0
The dataword was received without noise.
#0
1
The data was received with noise.
#1
PARITYE
The current received dataword contained in DATA[R9:R0] was received with a parity error.
14
1
read-only
0
The dataword was received without a parity error.
#0
1
The dataword was received with a parity error.
#1
R0T0
Read receive data buffer 0 or write transmit data buffer 0.
0
1
read-write
R1T1
Read receive data buffer 1 or write transmit data buffer 1.
1
1
read-write
R2T2
Read receive data buffer 2 or write transmit data buffer 2.
2
1
read-write
R3T3
Read receive data buffer 3 or write transmit data buffer 3.
3
1
read-write
R4T4
Read receive data buffer 4 or write transmit data buffer 4.
4
1
read-write
R5T5
Read receive data buffer 5 or write transmit data buffer 5.
5
1
read-write
R6T6
Read receive data buffer 6 or write transmit data buffer 6.
6
1
read-write
R7T7
Read receive data buffer 7 or write transmit data buffer 7.
7
1
read-write
R8T8
Read receive data buffer 8 or write transmit data buffer 8.
8
1
read-write
R9T9
Read receive data buffer 9 or write transmit data buffer 9.
9
1
read-write
RXEMPT
Receive Buffer Empty
12
1
read-only
0
Receive buffer contains valid data.
#0
1
Receive buffer is empty, data returned on read is not valid.
#1
MATCH
LPUART Match Address Register
0x10
32
read-write
n
0x0
0x0
MA1
Match Address 1
0
10
read-write
MA2
Match Address 2
16
10
read-write
STAT
LPUART Status Register
0x4
32
read-write
n
0x0
0x0
BRK13
Break Character Generation Length
26
1
read-write
0
Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
#0
1
Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).
#1
FE
Framing Error Flag
17
1
read-write
0
No framing error detected. This does not guarantee the framing is correct.
#0
1
Framing error.
#1
IDLE
Idle Line Flag
20
1
read-write
0
No idle line detected.
#0
1
Idle line was detected.
#1
LBKDE
LIN Break Detection Enable
25
1
read-write
0
Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
#0
1
Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
#1
LBKDIF
LIN Break Detect Interrupt Flag
31
1
read-write
0
No LIN break character has been detected.
#0
1
LIN break character has been detected.
#1
MA1F
Match 1 Flag
15
1
read-write
0
Received data is not equal to MA1
#0
1
Received data is equal to MA1
#1
MA2F
Match 2 Flag
14
1
read-write
0
Received data is not equal to MA2
#0
1
Received data is equal to MA2
#1
MSBF
MSB First
29
1
read-write
0
LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
#0
1
MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
#1
NF
Noise Flag
18
1
read-write
0
No noise detected.
#0
1
Noise detected in the received character in LPUART_DATA.
#1
OR
Receiver Overrun Flag
19
1
read-write
0
No overrun.
#0
1
Receive overrun (new LPUART data lost).
#1
PF
Parity Error Flag
16
1
read-write
0
No parity error.
#0
1
Parity error.
#1
RAF
Receiver Active Flag
24
1
read-only
0
LPUART receiver idle waiting for a start bit.
#0
1
LPUART receiver active (LPUART_RX input not idle).
#1
RDRF
Receive Data Register Full Flag
21
1
read-only
0
Receive data buffer empty.
#0
1
Receive data buffer full.
#1
RWUID
Receive Wake Up Idle Detect
27
1
read-write
0
During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match.
#0
1
During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match.
#1
RXEDGIF
LPUART_RX Pin Active Edge Interrupt Flag
30
1
read-write
0
No active edge on the receive pin has occurred.
#0
1
An active edge on the receive pin has occurred.
#1
RXINV
Receive Data Inversion
28
1
read-write
0
Receive data not inverted.
#0
1
Receive data inverted.
#1
TC
Transmission Complete Flag
22
1
read-only
0
Transmitter active (sending data, a preamble, or a break).
#0
1
Transmitter idle (transmission activity complete).
#1
TDRE
Transmit Data Register Empty Flag
23
1
read-only
0
Transmit data buffer full.
#0
1
Transmit data buffer empty.
#1
MCG
Multipurpose Clock Generator Lite
MCG
0x0
0x0
0x19
registers
n
C1
MCG Control Register 1
0x0
8
read-write
n
0x0
0x0
CLKS
Clock Source Select
6
2
read-write
00
Selects HIRC clock as the main clock source. This is HIRC mode.
#00
01
Selects LIRC clock as the main clock source. This is LIRC2M or LIRC8M mode.
#01
10
Selects external clock as the main clock source. This is EXT mode.
#10
11
Reserved. Writing 11 takes no effect.
#11
IRCLKEN
Internal Reference Clock Enable
1
1
read-write
0
LIRC is disabled.
#0
1
LIRC is enabled.
#1
IREFSTEN
Internal Reference Stop Enable
0
1
read-write
0
LIRC is disabled in Stop mode.
#0
1
LIRC is enabled in Stop mode, if IRCLKEN is set.
#1
C2
MCG Control Register 2
0x1
8
read-write
n
0x0
0x0
EREFS0
External Clock Source Select
2
1
read-write
0
External clock requested.
#0
1
Oscillator requested.
#1
HGO0
Crystal Oscillator Operation Mode Select
3
1
read-write
0
Configure crystal oscillator for low-power operation.
#0
1
Configure crystal oscillator for high-gain operation.
#1
IRCS
Low-frequency Internal Reference Clock Select
0
1
read-write
0
LIRC is in 2 MHz mode.
#0
1
LIRC is in 8 MHz mode.
#1
RANGE0
External Clock Source Frequency Range Select
4
2
read-write
00
Low frequency range selected for the crystal oscillator or the external clock source.
#00
01
High frequency range selected for the crystal oscillator or the external clock source.
#01
10
Very high frequency range selected for the crystal oscillator or the external clock source.
#10
11
Very high frequency range selected for the crystal oscillator or the external clock source. Same effect as 10.
#11
MC
MCG Miscellaneous Control Register
0x18
8
read-write
n
0x0
0x0
HIRCEN
High-frequency IRC Enable
7
1
read-write
0
HIRC source is not enabled.
#0
1
HIRC source is enabled.
#1
LIRC_DIV2
Second Low-frequency Internal Reference Clock Divider
0
3
read-write
000
Division factor is 1.
#000
001
Division factor is 2.
#001
010
Division factor is 4.
#010
011
Division factor is 8.
#011
100
Division factor is 16.
#100
101
Division factor is 32.
#101
110
Division factor is 64.
#110
111
Division factor is 128.
#111
S
MCG Status Register
0x6
8
read-only
n
0x0
0x0
CLKST
Clock Mode Status
2
2
read-only
00
HIRC clock is selected as the main clock source, and MCG_Lite works at HIRC mode.
#00
01
LIRC clock is selected as the main clock source, and MCG_Lite works at LIRC2M or LIRC8M mode.
#01
10
External clock is selected as the main clock source, and MCG_Lite works at EXT mode.
#10
OSCINIT0
OSC Initialization Status
1
1
read-only
0
OSC is not ready.
#0
1
OSC clock is ready.
#1
SC
MCG Status and Control Register
0x8
8
read-write
n
0x0
0x0
FCRDIV
Low-frequency Internal Reference Clock Divider
1
3
read-write
000
Division factor is 1.
#000
001
Division factor is 2.
#001
010
Division factor is 4.
#010
011
Division factor is 8.
#011
100
Division factor is 16.
#100
101
Division factor is 32.
#101
110
Division factor is 64.
#110
111
Division factor is 128.
#111
MCM
Core Platform Miscellaneous Control Module
MCM
0x0
0x8
0x3C
registers
n
CPO
Compute Operation Control Register
0x40
32
read-write
n
0x0
0x0
CPOACK
Compute Operation Acknowledge
1
1
read-only
0
Compute operation entry has not completed or compute operation exit has completed.
#0
1
Compute operation entry has completed or compute operation exit has not completed.
#1
CPOREQ
Compute Operation Request
0
1
read-write
0
Request is cleared.
#0
1
Request Compute Operation.
#1
CPOWOI
Compute Operation Wake-up on Interrupt
2
1
read-write
0
No effect.
#0
1
When set, the CPOREQ is cleared on any interrupt or exception vector fetch.
#1
PLACR
Platform Control Register
0xC
32
read-write
n
0x0
0x0
ARB
Arbitration select
9
1
read-write
0
Fixed-priority arbitration for the crossbar masters
#0
1
Round-robin arbitration for the crossbar masters
#1
CFCC
Clear Flash Controller Cache
10
1
read-write
DFCC
Disable Flash Controller Cache
13
1
read-write
0
Enable flash controller cache.
#0
1
Disable flash controller cache.
#1
DFCDA
Disable Flash Controller Data Caching
11
1
read-write
0
Enable flash controller data caching
#0
1
Disable flash controller data caching.
#1
DFCIC
Disable Flash Controller Instruction Caching
12
1
read-write
0
Enable flash controller instruction caching.
#0
1
Disable flash controller instruction caching.
#1
DFCS
Disable Flash Controller Speculation
15
1
read-write
0
Enable flash controller speculation.
#0
1
Disable flash controller speculation.
#1
EFDS
Enable Flash Data Speculation
14
1
read-write
0
Disable flash data speculation.
#0
1
Enable flash data speculation.
#1
ESFC
Enable Stalling Flash Controller
16
1
read-write
0
Disable stalling flash controller when flash is busy.
#0
1
Enable stalling flash controller when flash is busy.
#1
PLAMC
Crossbar Switch (AXBS) Master Configuration
0xA
16
read-only
n
0x0
0x0
AMC
Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
0
8
read-only
0
A bus master connection to AXBS input port n is absent
#0
1
A bus master connection to AXBS input port n is present
#1
PLASC
Crossbar Switch (AXBS) Slave Configuration
0x8
16
read-only
n
0x0
0x0
ASC
Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
0
8
read-only
0
A bus slave connection to AXBS input port n is absent.
#0
1
A bus slave connection to AXBS input port n is present.
#1
MTB
Micro Trace Buffer
MTB
0x0
0x0
0x1000
registers
n
AUTHSTAT
Authentication Status Register
0xFB8
32
read-only
n
0x0
0x0
BIT0
Connected to DBGEN.
0
1
read-only
BIT2
BIT2
2
1
read-only
BASE
MTB Base Register
0xC
32
read-only
n
0x0
0x0
BASEADDR
BASEADDR
0
32
read-only
COMPID0
Component ID Register
0x1FE0
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID1
Component ID Register
0x2FD4
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID2
Component ID Register
0x3FCC
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID3
Component ID Register
0x4FC8
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
DEVICEARCH
Device Architecture Register
0xFBC
32
read-only
n
0x0
0x0
DEVICEARCH
DEVICEARCH
0
32
read-only
DEVICECFG
Device Configuration Register
0xFC8
32
read-only
n
0x0
0x0
DEVICECFG
DEVICECFG
0
32
read-only
DEVICETYPID
Device Type Identifier Register
0xFCC
32
read-only
n
0x0
0x0
DEVICETYPID
DEVICETYPID
0
32
read-only
FLOW
MTB Flow Register
0x8
32
read-write
n
0x0
0x0
AUTOHALT
AUTOHALT
1
1
read-write
AUTOSTOP
AUTOSTOP
0
1
read-write
WATERMARK
WATERMARK[28:0]
3
29
read-write
LOCKACCESS
Lock Access Register
0xFB0
32
read-only
n
0x0
0x0
LOCKACCESS
Hardwired to 0x0000_0000
0
32
read-only
LOCKSTAT
Lock Status Register
0xFB4
32
read-only
n
0x0
0x0
LOCKSTAT
LOCKSTAT
0
32
read-only
MASTER
MTB Master Register
0x4
32
read-write
n
0x0
0x0
EN
Main Trace Enable
31
1
read-write
HALTREQ
Halt Request
9
1
read-write
MASK
Mask
0
5
read-write
RAMPRIV
RAM Privilege
8
1
read-write
SFRWPRIV
Special Function Register Write Privilege
7
1
read-write
TSTARTEN
Trace Start Input Enable
5
1
read-write
TSTOPEN
Trace Stop Input Enable
6
1
read-write
MODECTRL
Integration Mode Control Register
0xF00
32
read-only
n
0x0
0x0
MODECTRL
MODECTRL
0
32
read-only
PERIPHID0
Peripheral ID Register
0x5F08
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID1
Peripheral ID Register
0x6EEC
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID2
Peripheral ID Register
0x7ED4
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID3
Peripheral ID Register
0x8EC0
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID4
Peripheral ID Register
0x1FA0
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID5
Peripheral ID Register
0x2F74
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID6
Peripheral ID Register
0x3F4C
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID7
Peripheral ID Register
0x4F28
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
POSITION
MTB Position Register
0x0
32
read-write
n
0x0
0x0
POINTER
Trace Packet Address Pointer[28:0]
3
29
read-write
WRAP
WRAP
2
1
read-write
TAGCLEAR
Claim TAG Clear Register
0xFA4
32
read-only
n
0x0
0x0
TAGCLEAR
TAGCLEAR
0
32
read-only
TAGSET
Claim TAG Set Register
0xFA0
32
read-only
n
0x0
0x0
TAGSET
TAGSET
0
32
read-only
MTBDWT
MTB data watchpoint and trace
MTBDWT
0x0
0x0
0x1000
registers
n
COMP0
MTB_DWT Comparator Register
0x40
32
read-write
n
0x0
0x0
COMP
Reference value for comparison
0
32
read-write
COMP1
MTB_DWT Comparator Register
0x70
32
read-write
n
0x0
0x0
COMP
Reference value for comparison
0
32
read-write
COMPID0
Component ID Register
0x1FE0
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID1
Component ID Register
0x2FD4
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID2
Component ID Register
0x3FCC
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID3
Component ID Register
0x4FC8
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
CTRL
MTB DWT Control Register
0x0
32
read-only
n
0x0
0x0
DWTCFGCTRL
DWT configuration controls
0
28
read-only
NUMCMP
Number of comparators
28
4
read-only
DEVICECFG
Device Configuration Register
0xFC8
32
read-only
n
0x0
0x0
DEVICECFG
DEVICECFG
0
32
read-only
DEVICETYPID
Device Type Identifier Register
0xFCC
32
read-only
n
0x0
0x0
DEVICETYPID
DEVICETYPID
0
32
read-only
FCT0
MTB_DWT Comparator Function Register 0
0x28
32
read-write
n
0x0
0x0
DATAVADDR0
Data Value Address 0
12
4
read-write
DATAVMATCH
Data Value Match
8
1
read-write
0
Perform address comparison.
#0
1
Perform data value comparison.
#1
DATAVSIZE
Data Value Size
10
2
read-write
00
Byte.
#00
01
Halfword.
#01
10
Word.
#10
11
Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.
#11
FUNCTION
Function
0
4
read-write
000
Disabled.
#0000
100
Instruction fetch.
#0100
101
Data operand read.
#0101
110
Data operand write.
#0110
111
Data operand (read + write).
#0111
MATCHED
Comparator match
24
1
read-only
0
No match.
#0
1
Match occurred.
#1
FCT1
MTB_DWT Comparator Function Register 1
0x38
32
read-write
n
0x0
0x0
FUNCTION
Function
0
4
read-write
000
Disabled.
#0000
100
Instruction fetch.
#0100
101
Data operand read.
#0101
110
Data operand write.
#0110
111
Data operand (read + write).
#0111
MATCHED
Comparator match
24
1
read-only
0
No match.
#0
1
Match occurred.
#1
MASK0
MTB_DWT Comparator Mask Register
0x48
32
read-write
n
0x0
0x0
MASK
MASK
0
5
read-write
MASK1
MTB_DWT Comparator Mask Register
0x7C
32
read-write
n
0x0
0x0
MASK
MASK
0
5
read-write
PERIPHID0
Peripheral ID Register
0x5F08
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID1
Peripheral ID Register
0x6EEC
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID2
Peripheral ID Register
0x7ED4
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID3
Peripheral ID Register
0x8EC0
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID4
Peripheral ID Register
0x1FA0
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID5
Peripheral ID Register
0x2F74
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID6
Peripheral ID Register
0x3F4C
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID7
Peripheral ID Register
0x4F28
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
TBCTRL
MTB_DWT Trace Buffer Control Register
0x200
32
read-write
n
0x0
0x0
ACOMP0
Action based on Comparator 0 match
0
1
read-write
0
Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED].
#0
1
Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED].
#1
ACOMP1
Action based on Comparator 1 match
1
1
read-write
0
Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED].
#0
1
Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED].
#1
NUMCOMP
Number of Comparators
28
4
read-only
NVIC
Nested Vectored Interrupt Controller
NVIC
0x0
0x0
0x320
registers
n
ICER
Interrupt Clear Enable Register
0x80
32
read-write
n
0x0
0x0
CLRENA0
DMA channel 0 transfer complete interrupt clear-enable bit
0
1
read-write
0
write: no effect; read: DMA channel 0 transfer complete interrupt disabled
#0
1
write: disable DMA channel 0 transfer complete interrupt; read: DMA channel 0 transfer complete interrupt enabled
#1
CLRENA1
DMA channel 1 transfer complete interrupt clear-enable bit
1
1
read-write
0
write: no effect; read: DMA channel 1 transfer complete interrupt disabled
#0
1
write: disable DMA channel 1 transfer complete interrupt; read: DMA channel 1 transfer complete interrupt enabled
#1
CLRENA10
Serial Peripheral Interface 0 interrupt clear-enable bit
10
1
read-write
0
write: no effect; read: Serial Peripheral Interface 0 interrupt disabled
#0
1
write: disable Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt enabled
#1
CLRENA11
Serial Peripheral Interface 1 interrupt clear-enable bit
11
1
read-write
0
write: no effect; read: Serial Peripheral Interface 1 interrupt disabled
#0
1
write: disable Serial Peripheral Interface 1 interrupt; read: Serial Peripheral Interface 1 interrupt enabled
#1
CLRENA12
LPUART0 status and error interrupt clear-enable bit
12
1
read-write
0
write: no effect; read: LPUART0 status and error interrupt disabled
#0
1
write: disable LPUART0 status and error interrupt; read: LPUART0 status and error interrupt enabled
#1
CLRENA13
LPUART1 status and error interrupt clear-enable bit
13
1
read-write
0
write: no effect; read: LPUART1 status and error interrupt disabled
#0
1
write: disable LPUART1 status and error interrupt; read: LPUART1 status and error interrupt enabled
#1
CLRENA14
UART2 or FLEXIO interrupt clear-enable bit
14
1
read-write
0
write: no effect; read: UART2 or FLEXIO interrupt disabled
#0
1
write: disable UART2 or FLEXIO interrupt; read: UART2 or FLEXIO interrupt enabled
#1
CLRENA15
Analog-to-Digital Converter 0 interrupt clear-enable bit
15
1
read-write
0
write: no effect; read: Analog-to-Digital Converter 0 interrupt disabled
#0
1
write: disable Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt enabled
#1
CLRENA16
Comparator 0 interrupt clear-enable bit
16
1
read-write
0
write: no effect; read: Comparator 0 interrupt disabled
#0
1
write: disable Comparator 0 interrupt; read: Comparator 0 interrupt enabled
#1
CLRENA17
Timer/PWM module 0 interrupt clear-enable bit
17
1
read-write
0
write: no effect; read: Timer/PWM module 0 interrupt disabled
#0
1
write: disable Timer/PWM module 0 interrupt; read: Timer/PWM module 0 interrupt enabled
#1
CLRENA18
Timer/PWM module 1 interrupt clear-enable bit
18
1
read-write
0
write: no effect; read: Timer/PWM module 1 interrupt disabled
#0
1
write: disable Timer/PWM module 1 interrupt; read: Timer/PWM module 1 interrupt enabled
#1
CLRENA19
Timer/PWM module 2 interrupt clear-enable bit
19
1
read-write
0
write: no effect; read: Timer/PWM module 2 interrupt disabled
#0
1
write: disable Timer/PWM module 2 interrupt; read: Timer/PWM module 2 interrupt enabled
#1
CLRENA2
DMA channel 2 transfer complete interrupt clear-enable bit
2
1
read-write
0
write: no effect; read: DMA channel 2 transfer complete interrupt disabled
#0
1
write: disable DMA channel 2 transfer complete interrupt; read: DMA channel 2 transfer complete interrupt enabled
#1
CLRENA20
Real-time counter interrupt clear-enable bit
20
1
read-write
0
write: no effect; read: Real-time counter interrupt disabled
#0
1
write: disable Real-time counter interrupt; read: Real-time counter interrupt enabled
#1
CLRENA21
RTC seconds interrupt clear-enable bit
21
1
read-write
0
write: no effect; read: RTC seconds interrupt disabled
#0
1
write: disable RTC seconds interrupt; read: RTC seconds interrupt enabled
#1
CLRENA22
Periodic Interrupt Timer interrupt clear-enable bit
22
1
read-write
0
write: no effect; read: Periodic Interrupt Timer interrupt disabled
#0
1
write: disable Periodic Interrupt Timer interrupt; read: Periodic Interrupt Timer interrupt enabled
#1
CLRENA23
Reserved iv 39 interrupt clear-enable bit
23
1
read-write
0
write: no effect; read: Reserved iv 39 interrupt disabled
#0
1
write: disable Reserved iv 39 interrupt; read: Reserved iv 39 interrupt enabled
#1
CLRENA24
Universal Serial Bus interrupt clear-enable bit
24
1
read-write
0
write: no effect; read: Universal Serial Bus interrupt disabled
#0
1
write: disable Universal Serial Bus interrupt; read: Universal Serial Bus interrupt enabled
#1
CLRENA25
Digital to Analog Converter interrupt clear-enable bit
25
1
read-write
0
write: no effect; read: Digital to Analog Converter interrupt disabled
#0
1
write: disable Digital to Analog Converter interrupt; read: Digital to Analog Converter interrupt enabled
#1
CLRENA26
Reserved iv 42 interrupt clear-enable bit
26
1
read-write
0
write: no effect; read: Reserved iv 42 interrupt disabled
#0
1
write: disable Reserved iv 42 interrupt; read: Reserved iv 42 interrupt enabled
#1
CLRENA27
Reserved iv 43 interrupt clear-enable bit
27
1
read-write
0
write: no effect; read: Reserved iv 43 interrupt disabled
#0
1
write: disable Reserved iv 43 interrupt; read: Reserved iv 43 interrupt enabled
#1
CLRENA28
Low-Power Timer interrupt clear-enable bit
28
1
read-write
0
write: no effect; read: Low-Power Timer interrupt disabled
#0
1
write: disable Low-Power Timer interrupt; read: Low-Power Timer interrupt enabled
#1
CLRENA29
LCD interrupt clear-enable bit
29
1
read-write
0
write: no effect; read: LCD interrupt disabled
#0
1
write: disable LCD interrupt; read: LCD interrupt enabled
#1
CLRENA3
DMA channel 3 transfer complete interrupt clear-enable bit
3
1
read-write
0
write: no effect; read: DMA channel 3 transfer complete interrupt disabled
#0
1
write: disable DMA channel 3 transfer complete interrupt; read: DMA channel 3 transfer complete interrupt enabled
#1
CLRENA30
PORTA Pin detect interrupt clear-enable bit
30
1
read-write
0
write: no effect; read: PORTA Pin detect interrupt disabled
#0
1
write: disable PORTA Pin detect interrupt; read: PORTA Pin detect interrupt enabled
#1
CLRENA31
PORTC and PORTD Pin detect interrupt clear-enable bit
31
1
read-write
0
write: no effect; read: PORTC and PORTD Pin detect interrupt disabled
#0
1
write: disable PORTC and PORTD Pin detect interrupt; read: PORTC and PORTD Pin detect interrupt enabled
#1
CLRENA4
Reserved iv 20 interrupt clear-enable bit
4
1
read-write
0
write: no effect; read: Reserved iv 20 interrupt disabled
#0
1
write: disable Reserved iv 20 interrupt; read: Reserved iv 20 interrupt enabled
#1
CLRENA5
Command complete and read collision interrupt clear-enable bit
5
1
read-write
0
write: no effect; read: Command complete and read collision interrupt disabled
#0
1
write: disable Command complete and read collision interrupt; read: Command complete and read collision interrupt enabled
#1
CLRENA6
Low-voltage detect, low-voltage warning interrupt clear-enable bit
6
1
read-write
0
write: no effect; read: Low-voltage detect, low-voltage warning interrupt disabled
#0
1
write: disable Low-voltage detect, low-voltage warning interrupt; read: Low-voltage detect, low-voltage warning interrupt enabled
#1
CLRENA7
Low Leakage Wakeup interrupt clear-enable bit
7
1
read-write
0
write: no effect; read: Low Leakage Wakeup interrupt disabled
#0
1
write: disable Low Leakage Wakeup interrupt; read: Low Leakage Wakeup interrupt enabled
#1
CLRENA8
Inter-Integrated Circuit 0 interrupt clear-enable bit
8
1
read-write
0
write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled
#0
1
write: disable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled
#1
CLRENA9
Inter-Integrated Circuit 1 interrupt clear-enable bit
9
1
read-write
0
write: no effect; read: Inter-Integrated Circuit 1 interrupt disabled
#0
1
write: disable Inter-Integrated Circuit 1 interrupt; read: Inter-Integrated Circuit 1 interrupt enabled
#1
ICPR
Interrupt Clear Pending Register
0x180
32
read-write
n
0x0
0x0
CLRPEND0
DMA channel 0 transfer complete interrupt clear-pending bit
0
1
read-write
0
write: no effect; read: DMA channel 0 transfer complete interrupt is not pending
#0
1
write: removes pending state from the DMA channel 0 transfer complete interrupt; read: DMA channel 0 transfer complete interrupt is pending
#1
CLRPEND1
DMA channel 1 transfer complete interrupt clear-pending bit
1
1
read-write
0
write: no effect; read: DMA channel 1 transfer complete interrupt is not pending
#0
1
write: removes pending state from the DMA channel 1 transfer complete interrupt; read: DMA channel 1 transfer complete interrupt is pending
#1
CLRPEND10
Serial Peripheral Interface 0 interrupt clear-pending bit
10
1
read-write
0
write: no effect; read: Serial Peripheral Interface 0 interrupt is not pending
#0
1
write: removes pending state from the Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt is pending
#1
CLRPEND11
Serial Peripheral Interface 1 interrupt clear-pending bit
11
1
read-write
0
write: no effect; read: Serial Peripheral Interface 1 interrupt is not pending
#0
1
write: removes pending state from the Serial Peripheral Interface 1 interrupt; read: Serial Peripheral Interface 1 interrupt is pending
#1
CLRPEND12
LPUART0 status and error interrupt clear-pending bit
12
1
read-write
0
write: no effect; read: LPUART0 status and error interrupt is not pending
#0
1
write: removes pending state from the LPUART0 status and error interrupt; read: LPUART0 status and error interrupt is pending
#1
CLRPEND13
LPUART1 status and error interrupt clear-pending bit
13
1
read-write
0
write: no effect; read: LPUART1 status and error interrupt is not pending
#0
1
write: removes pending state from the LPUART1 status and error interrupt; read: LPUART1 status and error interrupt is pending
#1
CLRPEND14
UART2 or FLEXIO interrupt clear-pending bit
14
1
read-write
0
write: no effect; read: UART2 or FLEXIO interrupt is not pending
#0
1
write: removes pending state from the UART2 or FLEXIO interrupt; read: UART2 or FLEXIO interrupt is pending
#1
CLRPEND15
Analog-to-Digital Converter 0 interrupt clear-pending bit
15
1
read-write
0
write: no effect; read: Analog-to-Digital Converter 0 interrupt is not pending
#0
1
write: removes pending state from the Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt is pending
#1
CLRPEND16
Comparator 0 interrupt clear-pending bit
16
1
read-write
0
write: no effect; read: Comparator 0 interrupt is not pending
#0
1
write: removes pending state from the Comparator 0 interrupt; read: Comparator 0 interrupt is pending
#1
CLRPEND17
Timer/PWM module 0 interrupt clear-pending bit
17
1
read-write
0
write: no effect; read: Timer/PWM module 0 interrupt is not pending
#0
1
write: removes pending state from the Timer/PWM module 0 interrupt; read: Timer/PWM module 0 interrupt is pending
#1
CLRPEND18
Timer/PWM module 1 interrupt clear-pending bit
18
1
read-write
0
write: no effect; read: Timer/PWM module 1 interrupt is not pending
#0
1
write: removes pending state from the Timer/PWM module 1 interrupt; read: Timer/PWM module 1 interrupt is pending
#1
CLRPEND19
Timer/PWM module 2 interrupt clear-pending bit
19
1
read-write
0
write: no effect; read: Timer/PWM module 2 interrupt is not pending
#0
1
write: removes pending state from the Timer/PWM module 2 interrupt; read: Timer/PWM module 2 interrupt is pending
#1
CLRPEND2
DMA channel 2 transfer complete interrupt clear-pending bit
2
1
read-write
0
write: no effect; read: DMA channel 2 transfer complete interrupt is not pending
#0
1
write: removes pending state from the DMA channel 2 transfer complete interrupt; read: DMA channel 2 transfer complete interrupt is pending
#1
CLRPEND20
Real-time counter interrupt clear-pending bit
20
1
read-write
0
write: no effect; read: Real-time counter interrupt is not pending
#0
1
write: removes pending state from the Real-time counter interrupt; read: Real-time counter interrupt is pending
#1
CLRPEND21
RTC seconds interrupt clear-pending bit
21
1
read-write
0
write: no effect; read: RTC seconds interrupt is not pending
#0
1
write: removes pending state from the RTC seconds interrupt; read: RTC seconds interrupt is pending
#1
CLRPEND22
Periodic Interrupt Timer interrupt clear-pending bit
22
1
read-write
0
write: no effect; read: Periodic Interrupt Timer interrupt is not pending
#0
1
write: removes pending state from the Periodic Interrupt Timer interrupt; read: Periodic Interrupt Timer interrupt is pending
#1
CLRPEND23
Reserved iv 39 interrupt clear-pending bit
23
1
read-write
0
write: no effect; read: Reserved iv 39 interrupt is not pending
#0
1
write: removes pending state from the Reserved iv 39 interrupt; read: Reserved iv 39 interrupt is pending
#1
CLRPEND24
Universal Serial Bus interrupt clear-pending bit
24
1
read-write
0
write: no effect; read: Universal Serial Bus interrupt is not pending
#0
1
write: removes pending state from the Universal Serial Bus interrupt; read: Universal Serial Bus interrupt is pending
#1
CLRPEND25
Digital to Analog Converter interrupt clear-pending bit
25
1
read-write
0
write: no effect; read: Digital to Analog Converter interrupt is not pending
#0
1
write: removes pending state from the Digital to Analog Converter interrupt; read: Digital to Analog Converter interrupt is pending
#1
CLRPEND26
Reserved iv 42 interrupt clear-pending bit
26
1
read-write
0
write: no effect; read: Reserved iv 42 interrupt is not pending
#0
1
write: removes pending state from the Reserved iv 42 interrupt; read: Reserved iv 42 interrupt is pending
#1
CLRPEND27
Reserved iv 43 interrupt clear-pending bit
27
1
read-write
0
write: no effect; read: Reserved iv 43 interrupt is not pending
#0
1
write: removes pending state from the Reserved iv 43 interrupt; read: Reserved iv 43 interrupt is pending
#1
CLRPEND28
Low-Power Timer interrupt clear-pending bit
28
1
read-write
0
write: no effect; read: Low-Power Timer interrupt is not pending
#0
1
write: removes pending state from the Low-Power Timer interrupt; read: Low-Power Timer interrupt is pending
#1
CLRPEND29
LCD interrupt clear-pending bit
29
1
read-write
0
write: no effect; read: LCD interrupt is not pending
#0
1
write: removes pending state from the LCD interrupt; read: LCD interrupt is pending
#1
CLRPEND3
DMA channel 3 transfer complete interrupt clear-pending bit
3
1
read-write
0
write: no effect; read: DMA channel 3 transfer complete interrupt is not pending
#0
1
write: removes pending state from the DMA channel 3 transfer complete interrupt; read: DMA channel 3 transfer complete interrupt is pending
#1
CLRPEND30
PORTA Pin detect interrupt clear-pending bit
30
1
read-write
0
write: no effect; read: PORTA Pin detect interrupt is not pending
#0
1
write: removes pending state from the PORTA Pin detect interrupt; read: PORTA Pin detect interrupt is pending
#1
CLRPEND31
PORTC and PORTD Pin detect interrupt clear-pending bit
31
1
read-write
0
write: no effect; read: PORTC and PORTD Pin detect interrupt is not pending
#0
1
write: removes pending state from the PORTC and PORTD Pin detect interrupt; read: PORTC and PORTD Pin detect interrupt is pending
#1
CLRPEND4
Reserved iv 20 interrupt clear-pending bit
4
1
read-write
0
write: no effect; read: Reserved iv 20 interrupt is not pending
#0
1
write: removes pending state from the Reserved iv 20 interrupt; read: Reserved iv 20 interrupt is pending
#1
CLRPEND5
Command complete and read collision interrupt clear-pending bit
5
1
read-write
0
write: no effect; read: Command complete and read collision interrupt is not pending
#0
1
write: removes pending state from the Command complete and read collision interrupt; read: Command complete and read collision interrupt is pending
#1
CLRPEND6
Low-voltage detect, low-voltage warning interrupt clear-pending bit
6
1
read-write
0
write: no effect; read: Low-voltage detect, low-voltage warning interrupt is not pending
#0
1
write: removes pending state from the Low-voltage detect, low-voltage warning interrupt; read: Low-voltage detect, low-voltage warning interrupt is pending
#1
CLRPEND7
Low Leakage Wakeup interrupt clear-pending bit
7
1
read-write
0
write: no effect; read: Low Leakage Wakeup interrupt is not pending
#0
1
write: removes pending state from the Low Leakage Wakeup interrupt; read: Low Leakage Wakeup interrupt is pending
#1
CLRPEND8
Inter-Integrated Circuit 0 interrupt clear-pending bit
8
1
read-write
0
write: no effect; read: Inter-Integrated Circuit 0 interrupt is not pending
#0
1
write: removes pending state from the Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt is pending
#1
CLRPEND9
Inter-Integrated Circuit 1 interrupt clear-pending bit
9
1
read-write
0
write: no effect; read: Inter-Integrated Circuit 1 interrupt is not pending
#0
1
write: removes pending state from the Inter-Integrated Circuit 1 interrupt; read: Inter-Integrated Circuit 1 interrupt is pending
#1
IPR0
Interrupt Priority Register 0
0x300
32
read-write
n
0x0
0x0
PRI_0
Priority of the DMA channel 0 transfer complete interrupt
6
2
read-write
PRI_1
Priority of the DMA channel 1 transfer complete interrupt
14
2
read-write
PRI_2
Priority of the DMA channel 2 transfer complete interrupt
22
2
read-write
PRI_3
Priority of the DMA channel 3 transfer complete interrupt
30
2
read-write
IPR1
Interrupt Priority Register 1
0x304
32
read-write
n
0x0
0x0
PRI_4
Priority of the Reserved iv 20 interrupt
6
2
read-write
PRI_5
Priority of the Command complete and read collision interrupt
14
2
read-write
PRI_6
Priority of the Low-voltage detect, low-voltage warning interrupt
22
2
read-write
PRI_7
Priority of the Low Leakage Wakeup interrupt
30
2
read-write
IPR2
Interrupt Priority Register 2
0x308
32
read-write
n
0x0
0x0
PRI_10
Priority of the Serial Peripheral Interface 0 interrupt
22
2
read-write
PRI_11
Priority of the Serial Peripheral Interface 1 interrupt
30
2
read-write
PRI_8
Priority of the Inter-Integrated Circuit 0 interrupt
6
2
read-write
PRI_9
Priority of the Inter-Integrated Circuit 1 interrupt
14
2
read-write
IPR3
Interrupt Priority Register 3
0x30C
32
read-write
n
0x0
0x0
PRI_12
Priority of the LPUART0 status and error interrupt
6
2
read-write
PRI_13
Priority of the LPUART1 status and error interrupt
14
2
read-write
PRI_14
Priority of the UART2 or FLEXIO interrupt
22
2
read-write
PRI_15
Priority of the Analog-to-Digital Converter 0 interrupt
30
2
read-write
IPR4
Interrupt Priority Register 4
0x310
32
read-write
n
0x0
0x0
PRI_16
Priority of the Comparator 0 interrupt
6
2
read-write
PRI_17
Priority of the Timer/PWM module 0 interrupt
14
2
read-write
PRI_18
Priority of the Timer/PWM module 1 interrupt
22
2
read-write
PRI_19
Priority of the Timer/PWM module 2 interrupt
30
2
read-write
IPR5
Interrupt Priority Register 5
0x314
32
read-write
n
0x0
0x0
PRI_20
Priority of the Real-time counter interrupt
6
2
read-write
PRI_21
Priority of the RTC seconds interrupt
14
2
read-write
PRI_22
Priority of the Periodic Interrupt Timer interrupt
22
2
read-write
PRI_23
Priority of the Reserved iv 39 interrupt
30
2
read-write
IPR6
Interrupt Priority Register 6
0x318
32
read-write
n
0x0
0x0
PRI_24
Priority of the Universal Serial Bus interrupt
6
2
read-write
PRI_25
Priority of the Digital to Analog Converter interrupt
14
2
read-write
PRI_26
Priority of the Reserved iv 42 interrupt
22
2
read-write
PRI_27
Priority of the Reserved iv 43 interrupt
30
2
read-write
IPR7
Interrupt Priority Register 7
0x31C
32
read-write
n
0x0
0x0
PRI_28
Priority of the Low-Power Timer interrupt
6
2
read-write
PRI_29
Priority of the LCD interrupt
14
2
read-write
PRI_30
Priority of the PORTA Pin detect interrupt
22
2
read-write
PRI_31
Priority of the PORTC and PORTD Pin detect interrupt
30
2
read-write
ISER
Interrupt Set Enable Register
0x0
32
read-write
n
0x0
0x0
SETENA0
DMA channel 0 transfer complete interrupt set-enable bit
0
1
read-write
0
write: no effect; read: DMA channel 0 transfer complete interrupt disabled
#0
1
write: enable DMA channel 0 transfer complete interrupt; read: DMA channel 0 transfer complete interrupt enabled
#1
SETENA1
DMA channel 1 transfer complete interrupt set-enable bit
1
1
read-write
0
write: no effect; read: DMA channel 1 transfer complete interrupt disabled
#0
1
write: enable DMA channel 1 transfer complete interrupt; read: DMA channel 1 transfer complete interrupt enabled
#1
SETENA10
Serial Peripheral Interface 0 interrupt set-enable bit
10
1
read-write
0
write: no effect; read: Serial Peripheral Interface 0 interrupt disabled
#0
1
write: enable Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt enabled
#1
SETENA11
Serial Peripheral Interface 1 interrupt set-enable bit
11
1
read-write
0
write: no effect; read: Serial Peripheral Interface 1 interrupt disabled
#0
1
write: enable Serial Peripheral Interface 1 interrupt; read: Serial Peripheral Interface 1 interrupt enabled
#1
SETENA12
LPUART0 status and error interrupt set-enable bit
12
1
read-write
0
write: no effect; read: LPUART0 status and error interrupt disabled
#0
1
write: enable LPUART0 status and error interrupt; read: LPUART0 status and error interrupt enabled
#1
SETENA13
LPUART1 status and error interrupt set-enable bit
13
1
read-write
0
write: no effect; read: LPUART1 status and error interrupt disabled
#0
1
write: enable LPUART1 status and error interrupt; read: LPUART1 status and error interrupt enabled
#1
SETENA14
UART2 or FLEXIO interrupt set-enable bit
14
1
read-write
0
write: no effect; read: UART2 or FLEXIO interrupt disabled
#0
1
write: enable UART2 or FLEXIO interrupt; read: UART2 or FLEXIO interrupt enabled
#1
SETENA15
Analog-to-Digital Converter 0 interrupt set-enable bit
15
1
read-write
0
write: no effect; read: Analog-to-Digital Converter 0 interrupt disabled
#0
1
write: enable Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt enabled
#1
SETENA16
Comparator 0 interrupt set-enable bit
16
1
read-write
0
write: no effect; read: Comparator 0 interrupt disabled
#0
1
write: enable Comparator 0 interrupt; read: Comparator 0 interrupt enabled
#1
SETENA17
Timer/PWM module 0 interrupt set-enable bit
17
1
read-write
0
write: no effect; read: Timer/PWM module 0 interrupt disabled
#0
1
write: enable Timer/PWM module 0 interrupt; read: Timer/PWM module 0 interrupt enabled
#1
SETENA18
Timer/PWM module 1 interrupt set-enable bit
18
1
read-write
0
write: no effect; read: Timer/PWM module 1 interrupt disabled
#0
1
write: enable Timer/PWM module 1 interrupt; read: Timer/PWM module 1 interrupt enabled
#1
SETENA19
Timer/PWM module 2 interrupt set-enable bit
19
1
read-write
0
write: no effect; read: Timer/PWM module 2 interrupt disabled
#0
1
write: enable Timer/PWM module 2 interrupt; read: Timer/PWM module 2 interrupt enabled
#1
SETENA2
DMA channel 2 transfer complete interrupt set-enable bit
2
1
read-write
0
write: no effect; read: DMA channel 2 transfer complete interrupt disabled
#0
1
write: enable DMA channel 2 transfer complete interrupt; read: DMA channel 2 transfer complete interrupt enabled
#1
SETENA20
Real-time counter interrupt set-enable bit
20
1
read-write
0
write: no effect; read: Real-time counter interrupt disabled
#0
1
write: enable Real-time counter interrupt; read: Real-time counter interrupt enabled
#1
SETENA21
RTC seconds interrupt set-enable bit
21
1
read-write
0
write: no effect; read: RTC seconds interrupt disabled
#0
1
write: enable RTC seconds interrupt; read: RTC seconds interrupt enabled
#1
SETENA22
Periodic Interrupt Timer interrupt set-enable bit
22
1
read-write
0
write: no effect; read: Periodic Interrupt Timer interrupt disabled
#0
1
write: enable Periodic Interrupt Timer interrupt; read: Periodic Interrupt Timer interrupt enabled
#1
SETENA23
Reserved iv 39 interrupt set-enable bit
23
1
read-write
0
write: no effect; read: Reserved iv 39 interrupt disabled
#0
1
write: enable Reserved iv 39 interrupt; read: Reserved iv 39 interrupt enabled
#1
SETENA24
Universal Serial Bus interrupt set-enable bit
24
1
read-write
0
write: no effect; read: Universal Serial Bus interrupt disabled
#0
1
write: enable Universal Serial Bus interrupt; read: Universal Serial Bus interrupt enabled
#1
SETENA25
Digital to Analog Converter interrupt set-enable bit
25
1
read-write
0
write: no effect; read: Digital to Analog Converter interrupt disabled
#0
1
write: enable Digital to Analog Converter interrupt; read: Digital to Analog Converter interrupt enabled
#1
SETENA26
Reserved iv 42 interrupt set-enable bit
26
1
read-write
0
write: no effect; read: Reserved iv 42 interrupt disabled
#0
1
write: enable Reserved iv 42 interrupt; read: Reserved iv 42 interrupt enabled
#1
SETENA27
Reserved iv 43 interrupt set-enable bit
27
1
read-write
0
write: no effect; read: Reserved iv 43 interrupt disabled
#0
1
write: enable Reserved iv 43 interrupt; read: Reserved iv 43 interrupt enabled
#1
SETENA28
Low-Power Timer interrupt set-enable bit
28
1
read-write
0
write: no effect; read: Low-Power Timer interrupt disabled
#0
1
write: enable Low-Power Timer interrupt; read: Low-Power Timer interrupt enabled
#1
SETENA29
LCD interrupt set-enable bit
29
1
read-write
0
write: no effect; read: LCD interrupt disabled
#0
1
write: enable LCD interrupt; read: LCD interrupt enabled
#1
SETENA3
DMA channel 3 transfer complete interrupt set-enable bit
3
1
read-write
0
write: no effect; read: DMA channel 3 transfer complete interrupt disabled
#0
1
write: enable DMA channel 3 transfer complete interrupt; read: DMA channel 3 transfer complete interrupt enabled
#1
SETENA30
PORTA Pin detect interrupt set-enable bit
30
1
read-write
0
write: no effect; read: PORTA Pin detect interrupt disabled
#0
1
write: enable PORTA Pin detect interrupt; read: PORTA Pin detect interrupt enabled
#1
SETENA31
PORTC and PORTD Pin detect interrupt set-enable bit
31
1
read-write
0
write: no effect; read: PORTC and PORTD Pin detect interrupt disabled
#0
1
write: enable PORTC and PORTD Pin detect interrupt; read: PORTC and PORTD Pin detect interrupt enabled
#1
SETENA4
Reserved iv 20 interrupt set-enable bit
4
1
read-write
0
write: no effect; read: Reserved iv 20 interrupt disabled
#0
1
write: enable Reserved iv 20 interrupt; read: Reserved iv 20 interrupt enabled
#1
SETENA5
Command complete and read collision interrupt set-enable bit
5
1
read-write
0
write: no effect; read: Command complete and read collision interrupt disabled
#0
1
write: enable Command complete and read collision interrupt; read: Command complete and read collision interrupt enabled
#1
SETENA6
Low-voltage detect, low-voltage warning interrupt set-enable bit
6
1
read-write
0
write: no effect; read: Low-voltage detect, low-voltage warning interrupt disabled
#0
1
write: enable Low-voltage detect, low-voltage warning interrupt; read: Low-voltage detect, low-voltage warning interrupt enabled
#1
SETENA7
Low Leakage Wakeup interrupt set-enable bit
7
1
read-write
0
write: no effect; read: Low Leakage Wakeup interrupt disabled
#0
1
write: enable Low Leakage Wakeup interrupt; read: Low Leakage Wakeup interrupt enabled
#1
SETENA8
Inter-Integrated Circuit 0 interrupt set-enable bit
8
1
read-write
0
write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled
#0
1
write: enable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled
#1
SETENA9
Inter-Integrated Circuit 1 interrupt set-enable bit
9
1
read-write
0
write: no effect; read: Inter-Integrated Circuit 1 interrupt disabled
#0
1
write: enable Inter-Integrated Circuit 1 interrupt; read: Inter-Integrated Circuit 1 interrupt enabled
#1
ISPR
Interrupt Set Pending Register
0x100
32
read-write
n
0x0
0x0
SETPEND0
DMA channel 0 transfer complete interrupt set-pending bit
0
1
read-write
0
write: no effect; read: DMA channel 0 transfer complete interrupt is not pending
#0
1
write: changes the DMA channel 0 transfer complete interrupt state to pending; read: DMA channel 0 transfer complete interrupt is pending
#1
SETPEND1
DMA channel 1 transfer complete interrupt set-pending bit
1
1
read-write
0
write: no effect; read: DMA channel 1 transfer complete interrupt is not pending
#0
1
write: changes the DMA channel 1 transfer complete interrupt state to pending; read: DMA channel 1 transfer complete interrupt is pending
#1
SETPEND10
Serial Peripheral Interface 0 interrupt set-pending bit
10
1
read-write
0
write: no effect; read: Serial Peripheral Interface 0 interrupt is not pending
#0
1
write: changes the Serial Peripheral Interface 0 interrupt state to pending; read: Serial Peripheral Interface 0 interrupt is pending
#1
SETPEND11
Serial Peripheral Interface 1 interrupt set-pending bit
11
1
read-write
0
write: no effect; read: Serial Peripheral Interface 1 interrupt is not pending
#0
1
write: changes the Serial Peripheral Interface 1 interrupt state to pending; read: Serial Peripheral Interface 1 interrupt is pending
#1
SETPEND12
LPUART0 status and error interrupt set-pending bit
12
1
read-write
0
write: no effect; read: LPUART0 status and error interrupt is not pending
#0
1
write: changes the LPUART0 status and error interrupt state to pending; read: LPUART0 status and error interrupt is pending
#1
SETPEND13
LPUART1 status and error interrupt set-pending bit
13
1
read-write
0
write: no effect; read: LPUART1 status and error interrupt is not pending
#0
1
write: changes the LPUART1 status and error interrupt state to pending; read: LPUART1 status and error interrupt is pending
#1
SETPEND14
UART2 or FLEXIO interrupt set-pending bit
14
1
read-write
0
write: no effect; read: UART2 or FLEXIO interrupt is not pending
#0
1
write: changes the UART2 or FLEXIO interrupt state to pending; read: UART2 or FLEXIO interrupt is pending
#1
SETPEND15
Analog-to-Digital Converter 0 interrupt set-pending bit
15
1
read-write
0
write: no effect; read: Analog-to-Digital Converter 0 interrupt is not pending
#0
1
write: changes the Analog-to-Digital Converter 0 interrupt state to pending; read: Analog-to-Digital Converter 0 interrupt is pending
#1
SETPEND16
Comparator 0 interrupt set-pending bit
16
1
read-write
0
write: no effect; read: Comparator 0 interrupt is not pending
#0
1
write: changes the Comparator 0 interrupt state to pending; read: Comparator 0 interrupt is pending
#1
SETPEND17
Timer/PWM module 0 interrupt set-pending bit
17
1
read-write
0
write: no effect; read: Timer/PWM module 0 interrupt is not pending
#0
1
write: changes the Timer/PWM module 0 interrupt state to pending; read: Timer/PWM module 0 interrupt is pending
#1
SETPEND18
Timer/PWM module 1 interrupt set-pending bit
18
1
read-write
0
write: no effect; read: Timer/PWM module 1 interrupt is not pending
#0
1
write: changes the Timer/PWM module 1 interrupt state to pending; read: Timer/PWM module 1 interrupt is pending
#1
SETPEND19
Timer/PWM module 2 interrupt set-pending bit
19
1
read-write
0
write: no effect; read: Timer/PWM module 2 interrupt is not pending
#0
1
write: changes the Timer/PWM module 2 interrupt state to pending; read: Timer/PWM module 2 interrupt is pending
#1
SETPEND2
DMA channel 2 transfer complete interrupt set-pending bit
2
1
read-write
0
write: no effect; read: DMA channel 2 transfer complete interrupt is not pending
#0
1
write: changes the DMA channel 2 transfer complete interrupt state to pending; read: DMA channel 2 transfer complete interrupt is pending
#1
SETPEND20
Real-time counter interrupt set-pending bit
20
1
read-write
0
write: no effect; read: Real-time counter interrupt is not pending
#0
1
write: changes the Real-time counter interrupt state to pending; read: Real-time counter interrupt is pending
#1
SETPEND21
RTC seconds interrupt set-pending bit
21
1
read-write
0
write: no effect; read: RTC seconds interrupt is not pending
#0
1
write: changes the RTC seconds interrupt state to pending; read: RTC seconds interrupt is pending
#1
SETPEND22
Periodic Interrupt Timer interrupt set-pending bit
22
1
read-write
0
write: no effect; read: Periodic Interrupt Timer interrupt is not pending
#0
1
write: changes the Periodic Interrupt Timer interrupt state to pending; read: Periodic Interrupt Timer interrupt is pending
#1
SETPEND23
Reserved iv 39 interrupt set-pending bit
23
1
read-write
0
write: no effect; read: Reserved iv 39 interrupt is not pending
#0
1
write: changes the Reserved iv 39 interrupt state to pending; read: Reserved iv 39 interrupt is pending
#1
SETPEND24
Universal Serial Bus interrupt set-pending bit
24
1
read-write
0
write: no effect; read: Universal Serial Bus interrupt is not pending
#0
1
write: changes the Universal Serial Bus interrupt state to pending; read: Universal Serial Bus interrupt is pending
#1
SETPEND25
Digital to Analog Converter interrupt set-pending bit
25
1
read-write
0
write: no effect; read: Digital to Analog Converter interrupt is not pending
#0
1
write: changes the Digital to Analog Converter interrupt state to pending; read: Digital to Analog Converter interrupt is pending
#1
SETPEND26
Reserved iv 42 interrupt set-pending bit
26
1
read-write
0
write: no effect; read: Reserved iv 42 interrupt is not pending
#0
1
write: changes the Reserved iv 42 interrupt state to pending; read: Reserved iv 42 interrupt is pending
#1
SETPEND27
Reserved iv 43 interrupt set-pending bit
27
1
read-write
0
write: no effect; read: Reserved iv 43 interrupt is not pending
#0
1
write: changes the Reserved iv 43 interrupt state to pending; read: Reserved iv 43 interrupt is pending
#1
SETPEND28
Low-Power Timer interrupt set-pending bit
28
1
read-write
0
write: no effect; read: Low-Power Timer interrupt is not pending
#0
1
write: changes the Low-Power Timer interrupt state to pending; read: Low-Power Timer interrupt is pending
#1
SETPEND29
LCD interrupt set-pending bit
29
1
read-write
0
write: no effect; read: LCD interrupt is not pending
#0
1
write: changes the LCD interrupt state to pending; read: LCD interrupt is pending
#1
SETPEND3
DMA channel 3 transfer complete interrupt set-pending bit
3
1
read-write
0
write: no effect; read: DMA channel 3 transfer complete interrupt is not pending
#0
1
write: changes the DMA channel 3 transfer complete interrupt state to pending; read: DMA channel 3 transfer complete interrupt is pending
#1
SETPEND30
PORTA Pin detect interrupt set-pending bit
30
1
read-write
0
write: no effect; read: PORTA Pin detect interrupt is not pending
#0
1
write: changes the PORTA Pin detect interrupt state to pending; read: PORTA Pin detect interrupt is pending
#1
SETPEND31
PORTC and PORTD Pin detect interrupt set-pending bit
31
1
read-write
0
write: no effect; read: PORTC and PORTD Pin detect interrupt is not pending
#0
1
write: changes the PORTC and PORTD Pin detect interrupt state to pending; read: PORTC and PORTD Pin detect interrupt is pending
#1
SETPEND4
Reserved iv 20 interrupt set-pending bit
4
1
read-write
0
write: no effect; read: Reserved iv 20 interrupt is not pending
#0
1
write: changes the Reserved iv 20 interrupt state to pending; read: Reserved iv 20 interrupt is pending
#1
SETPEND5
Command complete and read collision interrupt set-pending bit
5
1
read-write
0
write: no effect; read: Command complete and read collision interrupt is not pending
#0
1
write: changes the Command complete and read collision interrupt state to pending; read: Command complete and read collision interrupt is pending
#1
SETPEND6
Low-voltage detect, low-voltage warning interrupt set-pending bit
6
1
read-write
0
write: no effect; read: Low-voltage detect, low-voltage warning interrupt is not pending
#0
1
write: changes the Low-voltage detect, low-voltage warning interrupt state to pending; read: Low-voltage detect, low-voltage warning interrupt is pending
#1
SETPEND7
Low Leakage Wakeup interrupt set-pending bit
7
1
read-write
0
write: no effect; read: Low Leakage Wakeup interrupt is not pending
#0
1
write: changes the Low Leakage Wakeup interrupt state to pending; read: Low Leakage Wakeup interrupt is pending
#1
SETPEND8
Inter-Integrated Circuit 0 interrupt set-pending bit
8
1
read-write
0
write: no effect; read: Inter-Integrated Circuit 0 interrupt is not pending
#0
1
write: changes the Inter-Integrated Circuit 0 interrupt state to pending; read: Inter-Integrated Circuit 0 interrupt is pending
#1
SETPEND9
Inter-Integrated Circuit 1 interrupt set-pending bit
9
1
read-write
0
write: no effect; read: Inter-Integrated Circuit 1 interrupt is not pending
#0
1
write: changes the Inter-Integrated Circuit 1 interrupt state to pending; read: Inter-Integrated Circuit 1 interrupt is pending
#1
OSC0
Oscillator
OSC0
0x0
0x0
0x1
registers
n
CR
OSC Control Register
0x0
8
read-write
n
0x0
0x0
ERCLKEN
External Reference Enable
7
1
read-write
0
External reference clock is inactive.
#0
1
External reference clock is enabled.
#1
EREFSTEN
External Reference Stop Enable
5
1
read-write
0
External reference clock is disabled in Stop mode.
#0
1
External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.
#1
SC16P
Oscillator 16 pF Capacitor Load Configure
0
1
read-write
0
Disable the selection.
#0
1
Add 16 pF capacitor to the oscillator load.
#1
SC2P
Oscillator 2 pF Capacitor Load Configure
3
1
read-write
0
Disable the selection.
#0
1
Add 2 pF capacitor to the oscillator load.
#1
SC4P
Oscillator 4 pF Capacitor Load Configure
2
1
read-write
0
Disable the selection.
#0
1
Add 4 pF capacitor to the oscillator load.
#1
SC8P
Oscillator 8 pF Capacitor Load Configure
1
1
read-write
0
Disable the selection.
#0
1
Add 8 pF capacitor to the oscillator load.
#1
PIT
Periodic Interrupt Timer
PIT
0x0
0x0
0x120
registers
n
PIT
22
CVAL0
Current Timer Value Register
0x208
32
read-only
n
0x0
0x0
TVL
Current Timer Value
0
32
read-only
CVAL1
Current Timer Value Register
0x31C
32
read-only
n
0x0
0x0
TVL
Current Timer Value
0
32
read-only
LDVAL0
Timer Load Value Register
0x200
32
read-write
n
0x0
0x0
TSV
Timer Start Value
0
32
read-write
LDVAL1
Timer Load Value Register
0x310
32
read-write
n
0x0
0x0
TSV
Timer Start Value
0
32
read-write
LTMR64H
PIT Upper Lifetime Timer Register
0xE0
32
read-only
n
0x0
0x0
LTH
Life Timer value
0
32
read-only
LTMR64L
PIT Lower Lifetime Timer Register
0xE4
32
read-only
n
0x0
0x0
LTL
Life Timer value
0
32
read-only
MCR
PIT Module Control Register
0x0
32
read-write
n
0x0
0x0
FRZ
Freeze
0
1
read-write
0
Timers continue to run in Debug mode.
#0
1
Timers are stopped in Debug mode.
#1
MDIS
Module Disable - (PIT section)
1
1
read-write
0
Clock for standard PIT timers is enabled.
#0
1
Clock for standard PIT timers is disabled.
#1
TCTRL0
Timer Control Register
0x210
32
read-write
n
0x0
0x0
CHN
Chain Mode
2
1
read-write
0
Timer is not chained.
#0
1
Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
#1
TEN
Timer Enable
0
1
read-write
0
Timer n is disabled.
#0
1
Timer n is enabled.
#1
TIE
Timer Interrupt Enable
1
1
read-write
0
Interrupt requests from Timer n are disabled.
#0
1
Interrupt will be requested whenever TIF is set.
#1
TCTRL1
Timer Control Register
0x328
32
read-write
n
0x0
0x0
CHN
Chain Mode
2
1
read-write
0
Timer is not chained.
#0
1
Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
#1
TEN
Timer Enable
0
1
read-write
0
Timer n is disabled.
#0
1
Timer n is enabled.
#1
TIE
Timer Interrupt Enable
1
1
read-write
0
Interrupt requests from Timer n are disabled.
#0
1
Interrupt will be requested whenever TIF is set.
#1
TFLG0
Timer Flag Register
0x218
32
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag
0
1
read-write
0
Timeout has not yet occurred.
#0
1
Timeout has occurred.
#1
TFLG1
Timer Flag Register
0x334
32
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag
0
1
read-write
0
Timeout has not yet occurred.
#0
1
Timeout has occurred.
#1
PMC
Power Management Controller
PMC
0x0
0x0
0x3
registers
n
PMC
6
LVDSC1
Low Voltage Detect Status And Control 1 register
0x0
8
read-write
n
0x0
0x0
LVDACK
Low-Voltage Detect Acknowledge
6
1
read-write
LVDF
Low-Voltage Detect Flag
7
1
read-only
0
Low-voltage event not detected
#0
1
Low-voltage event detected
#1
LVDIE
Low-Voltage Detect Interrupt Enable
5
1
read-write
0
Hardware interrupt disabled (use polling)
#0
1
Request a hardware interrupt when LVDF = 1
#1
LVDRE
Low-Voltage Detect Reset Enable
4
1
read-write
0
LVDF does not generate hardware resets
#0
1
Force an MCU reset when LVDF = 1
#1
LVDV
Low-Voltage Detect Voltage Select
0
2
read-write
0
Low trip point selected (V LVD = V LVDL )
#00
1
High trip point selected (V LVD = V LVDH )
#01
LVDSC2
Low Voltage Detect Status And Control 2 register
0x1
8
read-write
n
0x0
0x0
LVWACK
Low-Voltage Warning Acknowledge
6
1
read-write
LVWF
Low-Voltage Warning Flag
7
1
read-only
0
Low-voltage warning event not detected
#0
1
Low-voltage warning event detected
#1
LVWIE
Low-Voltage Warning Interrupt Enable
5
1
read-write
0
Hardware interrupt disabled (use polling)
#0
1
Request a hardware interrupt when LVWF = 1
#1
LVWV
Low-Voltage Warning Voltage Select
0
2
read-write
00
Low trip point selected (VLVW = VLVW1)
#00
01
Mid 1 trip point selected (VLVW = VLVW2)
#01
10
Mid 2 trip point selected (VLVW = VLVW3)
#10
11
High trip point selected (VLVW = VLVW4)
#11
REGSC
Regulator Status And Control register
0x2
8
read-write
n
0x0
0x0
ACKISO
Acknowledge Isolation
3
1
read-write
0
Peripherals and I/O pads are in normal run state.
#0
1
Certain peripherals and I/O pads are in an isolated and latched state.
#1
BGBE
Bandgap Buffer Enable
0
1
read-write
0
Bandgap buffer not enabled
#0
1
Bandgap buffer enabled
#1
BGEN
Bandgap Enable In VLPx Operation
4
1
read-write
0
Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
#0
1
Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
#1
REGONS
Regulator In Run Regulation Status
2
1
read-only
0
Regulator is in stop regulation or in transition to/from it
#0
1
Regulator is in run regulation
#1
PORTA
Pin Control and Interrupts
PORT
0x0
0x0
0xA4
registers
n
PORTA
30
GPCHR
Global Pin Control High Register
0x84
32
read-write
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
read-write
GPWE0
Global Pin Write Enable
16
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE1
Global Pin Write Enable
17
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE10
Global Pin Write Enable
26
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE11
Global Pin Write Enable
27
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE12
Global Pin Write Enable
28
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE13
Global Pin Write Enable
29
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE14
Global Pin Write Enable
30
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE15
Global Pin Write Enable
31
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE2
Global Pin Write Enable
18
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE3
Global Pin Write Enable
19
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE4
Global Pin Write Enable
20
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE5
Global Pin Write Enable
21
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE6
Global Pin Write Enable
22
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE7
Global Pin Write Enable
23
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE8
Global Pin Write Enable
24
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE9
Global Pin Write Enable
25
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCLR
Global Pin Control Low Register
0x80
32
read-write
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
read-write
GPWE0
Global Pin Write Enable
16
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE1
Global Pin Write Enable
17
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE10
Global Pin Write Enable
26
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE11
Global Pin Write Enable
27
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE12
Global Pin Write Enable
28
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE13
Global Pin Write Enable
29
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE14
Global Pin Write Enable
30
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE15
Global Pin Write Enable
31
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE2
Global Pin Write Enable
18
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE3
Global Pin Write Enable
19
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE4
Global Pin Write Enable
20
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE5
Global Pin Write Enable
21
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE6
Global Pin Write Enable
22
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE7
Global Pin Write Enable
23
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE8
Global Pin Write Enable
24
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE9
Global Pin Write Enable
25
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
n
0x0
0x0
ISF0
Interrupt Status Flag
0
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF1
Interrupt Status Flag
1
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF10
Interrupt Status Flag
10
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF11
Interrupt Status Flag
11
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF12
Interrupt Status Flag
12
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF13
Interrupt Status Flag
13
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF14
Interrupt Status Flag
14
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF15
Interrupt Status Flag
15
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF16
Interrupt Status Flag
16
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF17
Interrupt Status Flag
17
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF18
Interrupt Status Flag
18
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF19
Interrupt Status Flag
19
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF2
Interrupt Status Flag
2
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF20
Interrupt Status Flag
20
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF21
Interrupt Status Flag
21
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF22
Interrupt Status Flag
22
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF23
Interrupt Status Flag
23
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF24
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF25
Interrupt Status Flag
25
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF26
Interrupt Status Flag
26
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF27
Interrupt Status Flag
27
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF28
Interrupt Status Flag
28
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF29
Interrupt Status Flag
29
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF3
Interrupt Status Flag
3
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF30
Interrupt Status Flag
30
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF31
Interrupt Status Flag
31
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF4
Interrupt Status Flag
4
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF5
Interrupt Status Flag
5
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF6
Interrupt Status Flag
6
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF7
Interrupt Status Flag
7
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF8
Interrupt Status Flag
8
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF9
Interrupt Status Flag
9
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR0
Pin Control Register n
0x0
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR1
Pin Control Register n
0x4
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR10
Pin Control Register n
0x28
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR11
Pin Control Register n
0x2C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR12
Pin Control Register n
0x30
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR13
Pin Control Register n
0x34
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR14
Pin Control Register n
0x38
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR15
Pin Control Register n
0x3C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR16
Pin Control Register n
0x40
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR17
Pin Control Register n
0x44
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR18
Pin Control Register n
0x48
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR19
Pin Control Register n
0x4C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR2
Pin Control Register n
0x8
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR20
Pin Control Register n
0x50
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR21
Pin Control Register n
0x54
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR22
Pin Control Register n
0x58
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR23
Pin Control Register n
0x5C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR24
Pin Control Register n
0x60
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR25
Pin Control Register n
0x64
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR26
Pin Control Register n
0x68
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR27
Pin Control Register n
0x6C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR28
Pin Control Register n
0x70
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR29
Pin Control Register n
0x74
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR3
Pin Control Register n
0xC
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR30
Pin Control Register n
0x78
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR31
Pin Control Register n
0x7C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR4
Pin Control Register n
0x10
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR5
Pin Control Register n
0x14
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR6
Pin Control Register n
0x18
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR7
Pin Control Register n
0x1C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR8
Pin Control Register n
0x20
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR9
Pin Control Register n
0x24
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PORTB
Pin Control and Interrupts
PORT
0x0
0x0
0xA4
registers
n
GPCHR
Global Pin Control High Register
0x84
32
read-write
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
read-write
GPWE0
Global Pin Write Enable
16
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE1
Global Pin Write Enable
17
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE10
Global Pin Write Enable
26
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE11
Global Pin Write Enable
27
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE12
Global Pin Write Enable
28
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE13
Global Pin Write Enable
29
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE14
Global Pin Write Enable
30
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE15
Global Pin Write Enable
31
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE2
Global Pin Write Enable
18
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE3
Global Pin Write Enable
19
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE4
Global Pin Write Enable
20
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE5
Global Pin Write Enable
21
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE6
Global Pin Write Enable
22
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE7
Global Pin Write Enable
23
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE8
Global Pin Write Enable
24
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE9
Global Pin Write Enable
25
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCLR
Global Pin Control Low Register
0x80
32
read-write
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
read-write
GPWE0
Global Pin Write Enable
16
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE1
Global Pin Write Enable
17
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE10
Global Pin Write Enable
26
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE11
Global Pin Write Enable
27
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE12
Global Pin Write Enable
28
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE13
Global Pin Write Enable
29
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE14
Global Pin Write Enable
30
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE15
Global Pin Write Enable
31
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE2
Global Pin Write Enable
18
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE3
Global Pin Write Enable
19
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE4
Global Pin Write Enable
20
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE5
Global Pin Write Enable
21
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE6
Global Pin Write Enable
22
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE7
Global Pin Write Enable
23
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE8
Global Pin Write Enable
24
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE9
Global Pin Write Enable
25
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
n
0x0
0x0
ISF0
Interrupt Status Flag
0
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF1
Interrupt Status Flag
1
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF10
Interrupt Status Flag
10
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF11
Interrupt Status Flag
11
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF12
Interrupt Status Flag
12
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF13
Interrupt Status Flag
13
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF14
Interrupt Status Flag
14
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF15
Interrupt Status Flag
15
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF16
Interrupt Status Flag
16
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF17
Interrupt Status Flag
17
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF18
Interrupt Status Flag
18
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF19
Interrupt Status Flag
19
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF2
Interrupt Status Flag
2
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF20
Interrupt Status Flag
20
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF21
Interrupt Status Flag
21
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF22
Interrupt Status Flag
22
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF23
Interrupt Status Flag
23
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF24
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF25
Interrupt Status Flag
25
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF26
Interrupt Status Flag
26
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF27
Interrupt Status Flag
27
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF28
Interrupt Status Flag
28
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF29
Interrupt Status Flag
29
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF3
Interrupt Status Flag
3
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF30
Interrupt Status Flag
30
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF31
Interrupt Status Flag
31
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF4
Interrupt Status Flag
4
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF5
Interrupt Status Flag
5
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF6
Interrupt Status Flag
6
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF7
Interrupt Status Flag
7
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF8
Interrupt Status Flag
8
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF9
Interrupt Status Flag
9
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR0
Pin Control Register n
0x0
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR1
Pin Control Register n
0x4
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR10
Pin Control Register n
0x28
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR11
Pin Control Register n
0x2C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR12
Pin Control Register n
0x30
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR13
Pin Control Register n
0x34
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR14
Pin Control Register n
0x38
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR15
Pin Control Register n
0x3C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR16
Pin Control Register n
0x40
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR17
Pin Control Register n
0x44
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR18
Pin Control Register n
0x48
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR19
Pin Control Register n
0x4C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR2
Pin Control Register n
0x8
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR20
Pin Control Register n
0x50
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR21
Pin Control Register n
0x54
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR22
Pin Control Register n
0x58
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR23
Pin Control Register n
0x5C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR24
Pin Control Register n
0x60
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR25
Pin Control Register n
0x64
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR26
Pin Control Register n
0x68
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR27
Pin Control Register n
0x6C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR28
Pin Control Register n
0x70
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR29
Pin Control Register n
0x74
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR3
Pin Control Register n
0xC
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR30
Pin Control Register n
0x78
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR31
Pin Control Register n
0x7C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR4
Pin Control Register n
0x10
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR5
Pin Control Register n
0x14
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR6
Pin Control Register n
0x18
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR7
Pin Control Register n
0x1C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR8
Pin Control Register n
0x20
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR9
Pin Control Register n
0x24
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PORTC
Pin Control and Interrupts
PORT
0x0
0x0
0xA4
registers
n
PORTC_PORTD
31
GPCHR
Global Pin Control High Register
0x84
32
read-write
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
read-write
GPWE0
Global Pin Write Enable
16
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE1
Global Pin Write Enable
17
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE10
Global Pin Write Enable
26
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE11
Global Pin Write Enable
27
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE12
Global Pin Write Enable
28
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE13
Global Pin Write Enable
29
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE14
Global Pin Write Enable
30
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE15
Global Pin Write Enable
31
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE2
Global Pin Write Enable
18
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE3
Global Pin Write Enable
19
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE4
Global Pin Write Enable
20
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE5
Global Pin Write Enable
21
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE6
Global Pin Write Enable
22
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE7
Global Pin Write Enable
23
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE8
Global Pin Write Enable
24
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE9
Global Pin Write Enable
25
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCLR
Global Pin Control Low Register
0x80
32
read-write
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
read-write
GPWE0
Global Pin Write Enable
16
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE1
Global Pin Write Enable
17
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE10
Global Pin Write Enable
26
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE11
Global Pin Write Enable
27
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE12
Global Pin Write Enable
28
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE13
Global Pin Write Enable
29
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE14
Global Pin Write Enable
30
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE15
Global Pin Write Enable
31
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE2
Global Pin Write Enable
18
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE3
Global Pin Write Enable
19
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE4
Global Pin Write Enable
20
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE5
Global Pin Write Enable
21
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE6
Global Pin Write Enable
22
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE7
Global Pin Write Enable
23
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE8
Global Pin Write Enable
24
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE9
Global Pin Write Enable
25
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
n
0x0
0x0
ISF0
Interrupt Status Flag
0
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF1
Interrupt Status Flag
1
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF10
Interrupt Status Flag
10
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF11
Interrupt Status Flag
11
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF12
Interrupt Status Flag
12
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF13
Interrupt Status Flag
13
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF14
Interrupt Status Flag
14
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF15
Interrupt Status Flag
15
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF16
Interrupt Status Flag
16
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF17
Interrupt Status Flag
17
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF18
Interrupt Status Flag
18
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF19
Interrupt Status Flag
19
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF2
Interrupt Status Flag
2
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF20
Interrupt Status Flag
20
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF21
Interrupt Status Flag
21
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF22
Interrupt Status Flag
22
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF23
Interrupt Status Flag
23
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF24
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF25
Interrupt Status Flag
25
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF26
Interrupt Status Flag
26
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF27
Interrupt Status Flag
27
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF28
Interrupt Status Flag
28
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF29
Interrupt Status Flag
29
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF3
Interrupt Status Flag
3
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF30
Interrupt Status Flag
30
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF31
Interrupt Status Flag
31
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF4
Interrupt Status Flag
4
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF5
Interrupt Status Flag
5
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF6
Interrupt Status Flag
6
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF7
Interrupt Status Flag
7
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF8
Interrupt Status Flag
8
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF9
Interrupt Status Flag
9
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR0
Pin Control Register n
0x0
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR1
Pin Control Register n
0x4
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR10
Pin Control Register n
0x28
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR11
Pin Control Register n
0x2C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR12
Pin Control Register n
0x30
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR13
Pin Control Register n
0x34
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR14
Pin Control Register n
0x38
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR15
Pin Control Register n
0x3C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR16
Pin Control Register n
0x40
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR17
Pin Control Register n
0x44
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR18
Pin Control Register n
0x48
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR19
Pin Control Register n
0x4C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR2
Pin Control Register n
0x8
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR20
Pin Control Register n
0x50
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR21
Pin Control Register n
0x54
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR22
Pin Control Register n
0x58
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR23
Pin Control Register n
0x5C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR24
Pin Control Register n
0x60
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR25
Pin Control Register n
0x64
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR26
Pin Control Register n
0x68
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR27
Pin Control Register n
0x6C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR28
Pin Control Register n
0x70
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR29
Pin Control Register n
0x74
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR3
Pin Control Register n
0xC
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR30
Pin Control Register n
0x78
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR31
Pin Control Register n
0x7C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR4
Pin Control Register n
0x10
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR5
Pin Control Register n
0x14
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR6
Pin Control Register n
0x18
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR7
Pin Control Register n
0x1C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR8
Pin Control Register n
0x20
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR9
Pin Control Register n
0x24
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PORTD
Pin Control and Interrupts
PORT
0x0
0x0
0xA4
registers
n
PORTC_PORTD
31
GPCHR
Global Pin Control High Register
0x84
32
read-write
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
read-write
GPWE0
Global Pin Write Enable
16
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE1
Global Pin Write Enable
17
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE10
Global Pin Write Enable
26
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE11
Global Pin Write Enable
27
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE12
Global Pin Write Enable
28
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE13
Global Pin Write Enable
29
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE14
Global Pin Write Enable
30
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE15
Global Pin Write Enable
31
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE2
Global Pin Write Enable
18
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE3
Global Pin Write Enable
19
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE4
Global Pin Write Enable
20
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE5
Global Pin Write Enable
21
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE6
Global Pin Write Enable
22
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE7
Global Pin Write Enable
23
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE8
Global Pin Write Enable
24
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE9
Global Pin Write Enable
25
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCLR
Global Pin Control Low Register
0x80
32
read-write
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
read-write
GPWE0
Global Pin Write Enable
16
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE1
Global Pin Write Enable
17
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE10
Global Pin Write Enable
26
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE11
Global Pin Write Enable
27
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE12
Global Pin Write Enable
28
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE13
Global Pin Write Enable
29
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE14
Global Pin Write Enable
30
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE15
Global Pin Write Enable
31
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE2
Global Pin Write Enable
18
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE3
Global Pin Write Enable
19
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE4
Global Pin Write Enable
20
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE5
Global Pin Write Enable
21
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE6
Global Pin Write Enable
22
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE7
Global Pin Write Enable
23
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE8
Global Pin Write Enable
24
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE9
Global Pin Write Enable
25
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
n
0x0
0x0
ISF0
Interrupt Status Flag
0
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF1
Interrupt Status Flag
1
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF10
Interrupt Status Flag
10
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF11
Interrupt Status Flag
11
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF12
Interrupt Status Flag
12
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF13
Interrupt Status Flag
13
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF14
Interrupt Status Flag
14
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF15
Interrupt Status Flag
15
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF16
Interrupt Status Flag
16
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF17
Interrupt Status Flag
17
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF18
Interrupt Status Flag
18
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF19
Interrupt Status Flag
19
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF2
Interrupt Status Flag
2
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF20
Interrupt Status Flag
20
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF21
Interrupt Status Flag
21
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF22
Interrupt Status Flag
22
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF23
Interrupt Status Flag
23
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF24
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF25
Interrupt Status Flag
25
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF26
Interrupt Status Flag
26
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF27
Interrupt Status Flag
27
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF28
Interrupt Status Flag
28
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF29
Interrupt Status Flag
29
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF3
Interrupt Status Flag
3
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF30
Interrupt Status Flag
30
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF31
Interrupt Status Flag
31
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF4
Interrupt Status Flag
4
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF5
Interrupt Status Flag
5
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF6
Interrupt Status Flag
6
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF7
Interrupt Status Flag
7
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF8
Interrupt Status Flag
8
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF9
Interrupt Status Flag
9
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR0
Pin Control Register n
0x0
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR1
Pin Control Register n
0x4
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR10
Pin Control Register n
0x28
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR11
Pin Control Register n
0x2C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR12
Pin Control Register n
0x30
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR13
Pin Control Register n
0x34
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR14
Pin Control Register n
0x38
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR15
Pin Control Register n
0x3C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR16
Pin Control Register n
0x40
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR17
Pin Control Register n
0x44
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR18
Pin Control Register n
0x48
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR19
Pin Control Register n
0x4C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR2
Pin Control Register n
0x8
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR20
Pin Control Register n
0x50
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR21
Pin Control Register n
0x54
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR22
Pin Control Register n
0x58
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR23
Pin Control Register n
0x5C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR24
Pin Control Register n
0x60
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR25
Pin Control Register n
0x64
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR26
Pin Control Register n
0x68
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR27
Pin Control Register n
0x6C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR28
Pin Control Register n
0x70
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR29
Pin Control Register n
0x74
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR3
Pin Control Register n
0xC
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR30
Pin Control Register n
0x78
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR31
Pin Control Register n
0x7C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR4
Pin Control Register n
0x10
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR5
Pin Control Register n
0x14
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR6
Pin Control Register n
0x18
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR7
Pin Control Register n
0x1C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR8
Pin Control Register n
0x20
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR9
Pin Control Register n
0x24
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PORTE
Pin Control and Interrupts
PORT
0x0
0x0
0xA4
registers
n
GPCHR
Global Pin Control High Register
0x84
32
read-write
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
read-write
GPWE0
Global Pin Write Enable
16
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE1
Global Pin Write Enable
17
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE10
Global Pin Write Enable
26
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE11
Global Pin Write Enable
27
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE12
Global Pin Write Enable
28
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE13
Global Pin Write Enable
29
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE14
Global Pin Write Enable
30
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE15
Global Pin Write Enable
31
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE2
Global Pin Write Enable
18
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE3
Global Pin Write Enable
19
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE4
Global Pin Write Enable
20
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE5
Global Pin Write Enable
21
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE6
Global Pin Write Enable
22
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE7
Global Pin Write Enable
23
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE8
Global Pin Write Enable
24
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE9
Global Pin Write Enable
25
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCLR
Global Pin Control Low Register
0x80
32
read-write
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
read-write
GPWE0
Global Pin Write Enable
16
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE1
Global Pin Write Enable
17
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE10
Global Pin Write Enable
26
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE11
Global Pin Write Enable
27
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE12
Global Pin Write Enable
28
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE13
Global Pin Write Enable
29
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE14
Global Pin Write Enable
30
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE15
Global Pin Write Enable
31
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE2
Global Pin Write Enable
18
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE3
Global Pin Write Enable
19
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE4
Global Pin Write Enable
20
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE5
Global Pin Write Enable
21
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE6
Global Pin Write Enable
22
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE7
Global Pin Write Enable
23
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE8
Global Pin Write Enable
24
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPWE9
Global Pin Write Enable
25
1
read-write
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
n
0x0
0x0
ISF0
Interrupt Status Flag
0
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF1
Interrupt Status Flag
1
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF10
Interrupt Status Flag
10
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF11
Interrupt Status Flag
11
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF12
Interrupt Status Flag
12
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF13
Interrupt Status Flag
13
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF14
Interrupt Status Flag
14
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF15
Interrupt Status Flag
15
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF16
Interrupt Status Flag
16
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF17
Interrupt Status Flag
17
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF18
Interrupt Status Flag
18
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF19
Interrupt Status Flag
19
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF2
Interrupt Status Flag
2
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF20
Interrupt Status Flag
20
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF21
Interrupt Status Flag
21
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF22
Interrupt Status Flag
22
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF23
Interrupt Status Flag
23
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF24
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF25
Interrupt Status Flag
25
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF26
Interrupt Status Flag
26
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF27
Interrupt Status Flag
27
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF28
Interrupt Status Flag
28
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF29
Interrupt Status Flag
29
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF3
Interrupt Status Flag
3
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF30
Interrupt Status Flag
30
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF31
Interrupt Status Flag
31
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF4
Interrupt Status Flag
4
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF5
Interrupt Status Flag
5
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF6
Interrupt Status Flag
6
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF7
Interrupt Status Flag
7
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF8
Interrupt Status Flag
8
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
ISF9
Interrupt Status Flag
9
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR0
Pin Control Register n
0x0
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR1
Pin Control Register n
0x4
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR10
Pin Control Register n
0x28
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR11
Pin Control Register n
0x2C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR12
Pin Control Register n
0x30
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR13
Pin Control Register n
0x34
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR14
Pin Control Register n
0x38
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR15
Pin Control Register n
0x3C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR16
Pin Control Register n
0x40
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR17
Pin Control Register n
0x44
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR18
Pin Control Register n
0x48
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR19
Pin Control Register n
0x4C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR2
Pin Control Register n
0x8
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR20
Pin Control Register n
0x50
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR21
Pin Control Register n
0x54
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR22
Pin Control Register n
0x58
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR23
Pin Control Register n
0x5C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR24
Pin Control Register n
0x60
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR25
Pin Control Register n
0x64
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR26
Pin Control Register n
0x68
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR27
Pin Control Register n
0x6C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR28
Pin Control Register n
0x70
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR29
Pin Control Register n
0x74
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR3
Pin Control Register n
0xC
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR30
Pin Control Register n
0x78
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR31
Pin Control Register n
0x7C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR4
Pin Control Register n
0x10
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR5
Pin Control Register n
0x14
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR6
Pin Control Register n
0x18
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR7
Pin Control Register n
0x1C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR8
Pin Control Register n
0x20
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR9
Pin Control Register n
0x24
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-only
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt Status Flag (ISF) is disabled.
#0000
0001
ISF flag and DMA request on rising edge.
#0001
0010
ISF flag and DMA request on falling edge.
#0010
0011
ISF flag and DMA request on either edge.
#0011
1000
ISF flag and Interrupt when logic 0.
#1000
1001
ISF flag and Interrupt on rising-edge.
#1001
1010
ISF flag and Interrupt on falling-edge.
#1010
1011
ISF flag and Interrupt on either edge.
#1011
1100
ISF flag and Interrupt when logic 1.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (Alternative 0) (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-only
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-only
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-only
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1
SRE
Slew Rate Enable
2
1
read-only
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
RCM
Reset Control Module
RCM
0x0
0x0
0xA
registers
n
FM
Force Mode Register
0x6
8
read-write
n
0x0
0x0
FORCEROM
Force ROM Boot
1
2
read-write
00
No effect
#00
01
Force boot from ROM with RCM_MR[1] set.
#01
10
Force boot from ROM with RCM_MR[2] set.
#10
11
Force boot from ROM with RCM_MR[2:1] set.
#11
MR
Mode Register
0x7
8
read-write
n
0x0
0x0
BOOTROM
Boot ROM Configuration
1
2
read-write
00
Boot from Flash
#00
01
Boot from ROM due to BOOTCFG0 pin assertion
#01
10
Boot form ROM due to FOPT[7] configuration
#10
11
Boot from ROM due to both BOOTCFG0 pin assertion and FOPT[7] configuration
#11
RPFC
Reset Pin Filter Control register
0x4
8
read-write
n
0x0
0x0
RSTFLTSRW
Reset Pin Filter Select in Run and Wait Modes
0
2
read-write
00
All filtering disabled
#00
01
Bus clock filter enabled for normal operation
#01
10
LPO clock filter enabled for normal operation
#10
RSTFLTSS
Reset Pin Filter Select in Stop Mode
2
1
read-write
0
All filtering disabled
#0
1
LPO clock filter enabled
#1
RPFW
Reset Pin Filter Width register
0x5
8
read-write
n
0x0
0x0
RSTFLTSEL
Reset Pin Filter Bus Clock Select
0
5
read-write
00000
Bus clock filter count is 1
#00000
00001
Bus clock filter count is 2
#00001
00010
Bus clock filter count is 3
#00010
00011
Bus clock filter count is 4
#00011
00100
Bus clock filter count is 5
#00100
00101
Bus clock filter count is 6
#00101
00110
Bus clock filter count is 7
#00110
00111
Bus clock filter count is 8
#00111
01000
Bus clock filter count is 9
#01000
01001
Bus clock filter count is 10
#01001
01010
Bus clock filter count is 11
#01010
01011
Bus clock filter count is 12
#01011
01100
Bus clock filter count is 13
#01100
01101
Bus clock filter count is 14
#01101
01110
Bus clock filter count is 15
#01110
01111
Bus clock filter count is 16
#01111
10000
Bus clock filter count is 17
#10000
10001
Bus clock filter count is 18
#10001
10010
Bus clock filter count is 19
#10010
10011
Bus clock filter count is 20
#10011
10100
Bus clock filter count is 21
#10100
10101
Bus clock filter count is 22
#10101
10110
Bus clock filter count is 23
#10110
10111
Bus clock filter count is 24
#10111
11000
Bus clock filter count is 25
#11000
11001
Bus clock filter count is 26
#11001
11010
Bus clock filter count is 27
#11010
11011
Bus clock filter count is 28
#11011
11100
Bus clock filter count is 29
#11100
11101
Bus clock filter count is 30
#11101
11110
Bus clock filter count is 31
#11110
11111
Bus clock filter count is 32
#11111
SRS0
System Reset Status Register 0
0x0
8
read-only
n
0x0
0x0
LVD
Low-Voltage Detect Reset
1
1
read-only
0
Reset not caused by LVD trip or POR
#0
1
Reset caused by LVD trip or POR
#1
PIN
External Reset Pin
6
1
read-only
0
Reset not caused by external reset pin
#0
1
Reset caused by external reset pin
#1
POR
Power-On Reset
7
1
read-only
0
Reset not caused by POR
#0
1
Reset caused by POR
#1
WAKEUP
Low Leakage Wakeup Reset
0
1
read-only
0
Reset not caused by LLWU module wakeup source
#0
1
Reset caused by LLWU module wakeup source
#1
WDOG
Watchdog
5
1
read-only
0
Reset not caused by watchdog timeout
#0
1
Reset caused by watchdog timeout
#1
SRS1
System Reset Status Register 1
0x1
8
read-only
n
0x0
0x0
LOCKUP
Core Lockup
1
1
read-only
0
Reset not caused by core LOCKUP event
#0
1
Reset caused by core LOCKUP event
#1
MDM_AP
MDM-AP System Reset Request
3
1
read-only
0
Reset not caused by host debugger system setting of the System Reset Request bit
#0
1
Reset caused by host debugger system setting of the System Reset Request bit
#1
SACKERR
Stop Mode Acknowledge Error Reset
5
1
read-only
0
Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
#0
1
Reset caused by peripheral failure to acknowledge attempt to enter stop mode
#1
SW
Software
2
1
read-only
0
Reset not caused by software setting of SYSRESETREQ bit
#0
1
Reset caused by software setting of SYSRESETREQ bit
#1
SSRS0
Sticky System Reset Status Register 0
0x8
8
read-write
n
0x0
0x0
SLVD
Sticky Low-Voltage Detect Reset
1
1
read-write
0
Reset not caused by LVD trip or POR
#0
1
Reset caused by LVD trip or POR
#1
SPIN
Sticky External Reset Pin
6
1
read-write
0
Reset not caused by external reset pin
#0
1
Reset caused by external reset pin
#1
SPOR
Sticky Power-On Reset
7
1
read-write
0
Reset not caused by POR
#0
1
Reset caused by POR
#1
SWAKEUP
Sticky Low Leakage Wakeup Reset
0
1
read-write
0
Reset not caused by LLWU module wakeup source
#0
1
Reset caused by LLWU module wakeup source
#1
SWDOG
Sticky Watchdog
5
1
read-write
0
Reset not caused by watchdog timeout
#0
1
Reset caused by watchdog timeout
#1
SSRS1
Sticky System Reset Status Register 1
0x9
8
read-write
n
0x0
0x0
SLOCKUP
Sticky Core Lockup
1
1
read-write
0
Reset not caused by core LOCKUP event
#0
1
Reset caused by core LOCKUP event
#1
SMDM_AP
Sticky MDM-AP System Reset Request
3
1
read-write
0
Reset not caused by host debugger system setting of the System Reset Request bit
#0
1
Reset caused by host debugger system setting of the System Reset Request bit
#1
SSACKERR
Sticky Stop Mode Acknowledge Error Reset
5
1
read-write
0
Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
#0
1
Reset caused by peripheral failure to acknowledge attempt to enter stop mode
#1
SSW
Sticky Software
2
1
read-write
0
Reset not caused by software setting of SYSRESETREQ bit
#0
1
Reset caused by software setting of SYSRESETREQ bit
#1
RFSYS
System register file
RFSYS
0x0
0x0
0x20
registers
n
REG0
Register file register
0x0
32
read-write
n
0x0
0x0
HH
High higher byte
24
8
read-write
HL
High lower byte
16
8
read-write
LH
Low higher byte
8
8
read-write
LL
Low lower byte
0
8
read-write
REG1
Register file register
0x4
32
read-write
n
0x0
0x0
HH
High higher byte
24
8
read-write
HL
High lower byte
16
8
read-write
LH
Low higher byte
8
8
read-write
LL
Low lower byte
0
8
read-write
REG2
Register file register
0xC
32
read-write
n
0x0
0x0
HH
High higher byte
24
8
read-write
HL
High lower byte
16
8
read-write
LH
Low higher byte
8
8
read-write
LL
Low lower byte
0
8
read-write
REG3
Register file register
0x18
32
read-write
n
0x0
0x0
HH
High higher byte
24
8
read-write
HL
High lower byte
16
8
read-write
LH
Low higher byte
8
8
read-write
LL
Low lower byte
0
8
read-write
REG4
Register file register
0x28
32
read-write
n
0x0
0x0
HH
High higher byte
24
8
read-write
HL
High lower byte
16
8
read-write
LH
Low higher byte
8
8
read-write
LL
Low lower byte
0
8
read-write
REG5
Register file register
0x3C
32
read-write
n
0x0
0x0
HH
High higher byte
24
8
read-write
HL
High lower byte
16
8
read-write
LH
Low higher byte
8
8
read-write
LL
Low lower byte
0
8
read-write
REG6
Register file register
0x54
32
read-write
n
0x0
0x0
HH
High higher byte
24
8
read-write
HL
High lower byte
16
8
read-write
LH
Low higher byte
8
8
read-write
LL
Low lower byte
0
8
read-write
REG7
Register file register
0x70
32
read-write
n
0x0
0x0
HH
High higher byte
24
8
read-write
HL
High lower byte
16
8
read-write
LH
Low higher byte
8
8
read-write
LL
Low lower byte
0
8
read-write
ROM
System ROM
ROM
0x0
0x0
0x1000
registers
n
COMPID0
Component ID Register
0x1FE0
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID1
Component ID Register
0x2FD4
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID2
Component ID Register
0x3FCC
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID3
Component ID Register
0x4FC8
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
ENTRY0
Entry
0x0
32
read-only
n
0x0
0x0
ENTRY
ENTRY
0
32
read-only
ENTRY1
Entry
0x4
32
read-only
n
0x0
0x0
ENTRY
ENTRY
0
32
read-only
ENTRY2
Entry
0xC
32
read-only
n
0x0
0x0
ENTRY
ENTRY
0
32
read-only
PERIPHID0
Peripheral ID Register
0x5F08
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID1
Peripheral ID Register
0x6EEC
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID2
Peripheral ID Register
0x7ED4
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID3
Peripheral ID Register
0x8EC0
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID4
Peripheral ID Register
0x1FA0
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID5
Peripheral ID Register
0x2F74
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID6
Peripheral ID Register
0x3F4C
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID7
Peripheral ID Register
0x4F28
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
SYSACCESS
System Access Register
0xFCC
32
read-only
n
0x0
0x0
SYSACCESS
SYSACCESS
0
32
read-only
TABLEMARK
End of Table Marker Register
0xC
32
read-only
n
0x0
0x0
MARK
MARK
0
32
read-only
RTC
Secure Real Time Clock
RTC
0x0
0x0
0x20
registers
n
RTC
4
RTC_Seconds
21
CR
RTC Control Register
0x10
32
read-write
n
0x0
0x0
CLKO
Clock Output
9
1
read-write
0
The 32 kHz clock is output to other peripherals.
#0
1
The 32 kHz clock is not output to other peripherals.
#1
OSCE
Oscillator Enable
8
1
read-write
0
32.768 kHz oscillator is disabled.
#0
1
32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.
#1
SC16P
Oscillator 16pF Load Configure
10
1
read-write
0
Disable the load.
#0
1
Enable the additional load.
#1
SC2P
Oscillator 2pF Load Configure
13
1
read-write
0
Disable the load.
#0
1
Enable the additional load.
#1
SC4P
Oscillator 4pF Load Configure
12
1
read-write
0
Disable the load.
#0
1
Enable the additional load.
#1
SC8P
Oscillator 8pF Load Configure
11
1
read-write
0
Disable the load.
#0
1
Enable the additional load.
#1
SUP
Supervisor Access
2
1
read-write
0
Non-supervisor mode write accesses are not supported and generate a bus error.
#0
1
Non-supervisor mode write accesses are supported.
#1
SWR
Software Reset
0
1
read-write
0
No effect.
#0
1
Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it.
#1
UM
Update Mode
3
1
read-write
0
Registers cannot be written when locked.
#0
1
Registers can be written when locked under limited conditions.
#1
WPE
Wakeup Pin Enable
1
1
read-write
0
Wakeup pin is disabled.
#0
1
Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.
#1
WPS
Wakeup Pin Select
4
1
read-write
0
Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on.
#0
1
Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals.
#1
IER
RTC Interrupt Enable Register
0x1C
32
read-write
n
0x0
0x0
TAIE
Time Alarm Interrupt Enable
2
1
read-write
0
Time alarm flag does not generate an interrupt.
#0
1
Time alarm flag does generate an interrupt.
#1
TIIE
Time Invalid Interrupt Enable
0
1
read-write
0
Time invalid flag does not generate an interrupt.
#0
1
Time invalid flag does generate an interrupt.
#1
TOIE
Time Overflow Interrupt Enable
1
1
read-write
0
Time overflow flag does not generate an interrupt.
#0
1
Time overflow flag does generate an interrupt.
#1
TSIE
Time Seconds Interrupt Enable
4
1
read-write
0
Seconds interrupt is disabled.
#0
1
Seconds interrupt is enabled.
#1
WPON
Wakeup Pin On
7
1
read-write
0
No effect.
#0
1
If the wakeup pin is enabled, then the wakeup pin will assert.
#1
LR
RTC Lock Register
0x18
32
read-write
n
0x0
0x0
CRL
Control Register Lock
4
1
read-write
0
Control Register is locked and writes are ignored.
#0
1
Control Register is not locked and writes complete as normal.
#1
LRL
Lock Register Lock
6
1
read-write
0
Lock Register is locked and writes are ignored.
#0
1
Lock Register is not locked and writes complete as normal.
#1
SRL
Status Register Lock
5
1
read-write
0
Status Register is locked and writes are ignored.
#0
1
Status Register is not locked and writes complete as normal.
#1
TCL
Time Compensation Lock
3
1
read-write
0
Time Compensation Register is locked and writes are ignored.
#0
1
Time Compensation Register is not locked and writes complete as normal.
#1
SR
RTC Status Register
0x14
32
read-write
n
0x0
0x0
TAF
Time Alarm Flag
2
1
read-only
0
Time alarm has not occurred.
#0
1
Time alarm has occurred.
#1
TCE
Time Counter Enable
4
1
read-write
0
Time counter is disabled.
#0
1
Time counter is enabled.
#1
TIF
Time Invalid Flag
0
1
read-only
0
Time is valid.
#0
1
Time is invalid and time counter is read as zero.
#1
TOF
Time Overflow Flag
1
1
read-only
0
Time overflow has not occurred.
#0
1
Time overflow has occurred and time counter is read as zero.
#1
TAR
RTC Time Alarm Register
0x8
32
read-write
n
0x0
0x0
TAR
Time Alarm Register
0
32
read-write
TCR
RTC Time Compensation Register
0xC
32
read-write
n
0x0
0x0
CIC
Compensation Interval Counter
24
8
read-only
CIR
Compensation Interval Register
8
8
read-write
TCR
Time Compensation Register
0
8
read-write
00000000
Time Prescaler Register overflows every 32768 clock cycles.
#0
00000001
Time Prescaler Register overflows every 32767 clock cycles.
#1
10000000
Time Prescaler Register overflows every 32896 clock cycles.
#10000000
01111111
Time Prescaler Register overflows every 32641 clock cycles.
#1111111
11111111
Time Prescaler Register overflows every 32769 clock cycles.
#11111111
TCV
Time Compensation Value
16
8
read-only
TPR
RTC Time Prescaler Register
0x4
32
read-write
n
0x0
0x0
TPR
Time Prescaler Register
0
16
read-write
TSR
RTC Time Seconds Register
0x0
32
read-write
n
0x0
0x0
TSR
Time Seconds Register
0
32
read-write
SIM
System Integration Module
SIM
0x0
0x0
0x1108
registers
n
CLKDIV1
System Clock Divider Register 1
0x1044
32
read-write
n
0x0
0x0
OUTDIV1
Clock 1 Output Divider value
28
4
read-write
0000
Divide-by-1.
#0000
0001
Divide-by-2.
#0001
0010
Divide-by-3.
#0010
0011
Divide-by-4.
#0011
0100
Divide-by-5.
#0100
0101
Divide-by-6.
#0101
0110
Divide-by-7.
#0110
0111
Divide-by-8.
#0111
1000
Divide-by-9.
#1000
1001
Divide-by-10.
#1001
1010
Divide-by-11.
#1010
1011
Divide-by-12.
#1011
1100
Divide-by-13.
#1100
1101
Divide-by-14.
#1101
1110
Divide-by-15.
#1110
1111
Divide-by-16.
#1111
OUTDIV4
Clock 4 Output Divider value
16
3
read-write
000
Divide-by-1.
#000
001
Divide-by-2.
#001
010
Divide-by-3.
#010
011
Divide-by-4.
#011
100
Divide-by-5.
#100
101
Divide-by-6.
#101
110
Divide-by-7.
#110
111
Divide-by-8.
#111
COPC
COP Control Register
0x1100
32
read-write
n
0x0
0x0
COPCLKS
COP Clock Select
1
1
read-write
0
COP configured for short timeout
#0
1
COP configured for long timeout
#1
COPCLKSEL
COP Clock Select
6
2
read-write
00
LPO clock (1 kHz)
#00
01
MCGIRCLK
#01
10
OSCERCLK
#10
11
Bus clock
#11
COPDBGEN
COP Debug Enable
5
1
read-write
0
COP is disabled and the counter is reset in Debug mode
#0
1
COP is enabled in Debug mode
#1
COPSTPEN
COP Stop Enable
4
1
read-write
0
COP is disabled and the counter is reset in Stop modes
#0
1
COP is enabled in Stop modes
#1
COPT
COP Watchdog Timeout
2
2
read-write
00
COP disabled
#00
01
COP timeout after 25 cycles for short timeout or 213 cycles for long timeout
#01
10
COP timeout after 28 cycles for short timeout or 216 cycles for long timeout
#10
11
COP timeout after 210 cycles for short timeout or 218 cycles for long timeout
#11
COPW
COP Windowed Mode
0
1
read-write
0
Normal mode
#0
1
Windowed mode
#1
FCFG1
Flash Configuration Register 1
0x104C
32
read-write
n
0x0
0x0
FLASHDIS
Flash Disable
0
1
read-write
0
Flash is enabled.
#0
1
Flash is disabled.
#1
FLASHDOZE
Flash Doze
1
1
read-write
0
Flash remains enabled during Doze mode.
#0
1
Flash is disabled for the duration of Doze mode.
#1
PFSIZE
Program Flash Size
24
4
read-only
0000
8 KB of program flash memory, 1 KB protection region
#0000
0001
16 KB of program flash memory, 1 KB protection region
#0001
0011
32 KB of program flash memory, 1 KB protection region
#0011
0101
64 KB of program flash memory, 2 KB protection region
#0101
0111
128 KB of program flash memory, 4 KB protection region
#0111
1001
256 KB of program flash memory, 8 KB protection region
#1001
1111
256 KB of program flash memory, 8 KB protection region
#1111
FCFG2
Flash Configuration Register 2
0x1050
32
read-only
n
0x0
0x0
MAXADDR0
Max Address lock
24
7
read-only
MAXADDR1
This field concatenated with leading zeros plus the value of the MAXADDR0 field indicates the first invalid address of the second program flash block (flash block 1)
16
7
read-only
SCGC4
System Clock Gating Control Register 4
0x1034
32
read-write
n
0x0
0x0
CMP0
Comparator Clock Gate Control
19
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
I2C0
I2C0 Clock Gate Control
6
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
I2C1
I2C1 Clock Gate Control
7
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SPI0
SPI0 Clock Gate Control
22
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SPI1
SPI1 Clock Gate Control
23
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
UART2
UART2 Clock Gate Control
12
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
USBFS
USB Clock Gate Control
18
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
VREF
VREF Clock Gate Control
20
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SCGC5
System Clock Gating Control Register 5
0x1038
32
read-write
n
0x0
0x0
FLEXIO
FlexIO Module
31
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
LPTMR
Low Power Timer Access Control
0
1
read-write
0
Access disabled
#0
1
Access enabled
#1
LPUART0
LPUART0 Clock Gate Control
20
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
LPUART1
LPUART1 Clock Gate Control
21
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PORTA
Port A Clock Gate Control
9
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PORTB
Port B Clock Gate Control
10
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PORTC
Port C Clock Gate Control
11
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PORTD
Port D Clock Gate Control
12
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PORTE
Port E Clock Gate Control
13
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SLCD
Segment LCD Clock Gate Control
19
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SCGC6
System Clock Gating Control Register 6
0x103C
32
read-write
n
0x0
0x0
ADC0
ADC0 Clock Gate Control
27
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
DAC0
DAC0 Clock Gate Control
31
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
DMAMUX
DMA Mux Clock Gate Control
1
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
FTF
Flash Memory Clock Gate Control
0
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PIT
PIT Clock Gate Control
23
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
RTC
RTC Access Control
29
1
read-write
0
Access and interrupts disabled
#0
1
Access and interrupts enabled
#1
TPM0
TPM0 Clock Gate Control
24
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
TPM1
TPM1 Clock Gate Control
25
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
TPM2
TPM2 Clock Gate Control
26
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SCGC7
System Clock Gating Control Register 7
0x1040
32
read-write
n
0x0
0x0
DMA
DMA Clock Gate Control
8
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SDID
System Device Identification Register
0x1024
32
read-only
n
0x0
0x0
FAMID
Family ID
28
4
read-only
000
K32L3A
#0000
010
K32L2A
#0010
100
K32L2B
#0100
PINID
Pincount Identification
0
4
read-only
0010
32-pin
#0010
0100
48-pin
#0100
0101
64-pin
#0101
1011
Custom pinout (WLCSP)
#1011
REVID
Device Revision Number
12
4
read-only
SERIESID
Series ID
20
4
read-only
1
K32 L2 family
#0001
SRAMSIZE
System SRAM Size
16
4
read-only
101
16 KB
#0101
110
32 KB
#0110
SUBFAMID
Sub-Family ID
24
4
read-only
0
Dual core
#0000
1
Single core
#0001
SOPT1
System Options Register 1
0x0
32
read-write
n
0x0
0x0
OSC32KOUT
32K oscillator clock output
16
2
read-write
00
ERCLK32K is not output.
#00
01
ERCLK32K is output on PTE0.
#01
10
ERCLK32K is output on PTE26.
#10
OSC32KSEL
32K Oscillator Clock Select
18
2
read-write
00
System oscillator (OSC32KCLK)
#00
10
RTC_CLKIN
#10
11
LPO 1kHz
#11
USBREGEN
USB voltage regulator enable
31
1
read-write
0
USB voltage regulator is disabled.
#0
1
USB voltage regulator is enabled.
#1
USBSSTBY
USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes.
30
1
read-write
0
USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes.
#0
1
USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
#1
USBVSTBY
USB voltage regulator in standby mode during VLPR and VLPW modes
29
1
read-write
0
USB voltage regulator not in standby during VLPR and VLPW modes.
#0
1
USB voltage regulator in standby during VLPR and VLPW modes.
#1
SOPT1CFG
SOPT1 Configuration Register
0x4
32
read-write
n
0x0
0x0
URWE
USB voltage regulator enable write enable
24
1
read-write
0
SOPT1 USBREGEN cannot be written.
#0
1
SOPT1 USBREGEN can be written.
#1
USSWE
USB voltage regulator stop standby write enable
26
1
read-write
0
SOPT1 USBSSTB cannot be written.
#0
1
SOPT1 USBSSTB can be written.
#1
UVSWE
USB voltage regulator VLP standby write enable
25
1
read-write
0
SOPT1 USBVSTB cannot be written.
#0
1
SOPT1 USBVSTB can be written.
#1
SOPT2
System Options Register 2
0x1004
32
read-write
n
0x0
0x0
CLKOUTSEL
CLKOUT select
5
3
read-write
010
Bus clock
#010
011
LPO clock (1 kHz)
#011
100
LIRC_CLK
#100
110
OSCERCLK
#110
111
IRC48M clock (IRC48M clock can be output to PAD only when chip VDD is 2.7-3.6 V)
#111
FLEXIOSRC
FlexIO Module Clock Source Select
22
2
read-write
00
Clock disabled
#00
01
IRC48M clock
#01
10
OSCERCLK clock
#10
11
MCGIRCLK clock
#11
LPUART0SRC
LPUART0 Clock Source Select
26
2
read-write
00
Clock disabled
#00
01
IRC48M clock
#01
10
OSCERCLK clock
#10
11
MCGIRCLK clock
#11
LPUART1SRC
LPUART1 Clock Source Select
28
2
read-write
00
Clock disabled
#00
01
IRC48M clock
#01
10
OSCERCLK clock
#10
11
MCGIRCLK clock
#11
RTCCLKOUTSEL
RTC Clock Out Select
4
1
read-write
0
RTC 1 Hz clock is output on the RTC_CLKOUT pin.
#0
1
OSCERCLK clock is output on the RTC_CLKOUT pin.
#1
TPMSRC
TPM Clock Source Select
24
2
read-write
00
Clock disabled
#00
01
IRC48M clock
#01
10
OSCERCLK clock
#10
11
MCGIRCLK clock
#11
USBSRC
USB clock source select
18
1
read-write
0
External bypass clock (USB_CLKIN).
#0
1
IRC48M clock
#1
SOPT4
System Options Register 4
0x100C
32
read-write
n
0x0
0x0
TPM0CLKSEL
TPM0 External Clock Pin Select
24
1
read-write
0
TPM0 external clock driven by TPM_CLKIN0 pin.
#0
1
TPM0 external clock driven by TPM_CLKIN1 pin.
#1
TPM1CH0SRC
TPM1 channel 0 input capture source select
18
2
read-write
00
TPM1_CH0 signal
#00
01
CMP0 output
#01
11
USB start of frame pulse
#11
TPM1CLKSEL
TPM1 External Clock Pin Select
25
1
read-write
0
TPM1 external clock driven by TPM_CLKIN0 pin.
#0
1
TPM1 external clock driven by TPM_CLKIN1 pin.
#1
TPM2CH0SRC
TPM2 Channel 0 Input Capture Source Select
20
1
read-write
0
TPM2_CH0 signal
#0
1
CMP0 output
#1
TPM2CLKSEL
TPM2 External Clock Pin Select
26
1
read-write
0
TPM2 external clock driven by TPM_CLKIN0 pin.
#0
1
TPM2 external clock driven by TPM_CLKIN1 pin.
#1
SOPT5
System Options Register 5
0x1010
32
read-write
n
0x0
0x0
LPUART0ODE
LPUART0 Open Drain Enable
16
1
read-write
0
Open drain is disabled on LPUART0.
#0
1
Open drain is enabled on LPUART0.
#1
LPUART0RXSRC
LPUART0 Receive Data Source Select
2
1
read-write
0
LPUART_RX pin
#0
1
CMP0 output
#1
LPUART0TXSRC
LPUART0 Transmit Data Source Select
0
2
read-write
00
LPUART0_TX pin
#00
01
LPUART0_TX pin modulated with TPM1 channel 0 output
#01
10
LPUART0_TX pin modulated with TPM2 channel 0 output
#10
LPUART1ODE
LPUART1 Open Drain Enable
17
1
read-write
0
Open drain is disabled on LPUART1.
#0
1
Open drain is enabled on LPUART1
#1
LPUART1RXSRC
LPUART1 Receive Data Source Select
6
1
read-write
0
LPUART1_RX pin
#0
1
CMP0 output
#1
LPUART1TXSRC
LPUART1 Transmit Data Source Select
4
2
read-write
00
LPUART1_TX pin
#00
01
LPUART1_TX pin modulated with TPM1 channel 0 output
#01
10
LPUART1_TX pin modulated with TPM2 channel 0 output
#10
UART2ODE
UART2 Open Drain Enable
18
1
read-write
0
Open drain is disabled on UART2
#0
1
Open drain is enabled on UART2
#1
SOPT7
System Options Register 7
0x1018
32
read-write
n
0x0
0x0
ADC0ALTTRGEN
ADC0 Alternate Trigger Enable
7
1
read-write
0
ADC ADHWT trigger comes from TPM1 channel 0 and channel1. Prior to the assertion of TPM1 channel 0, a pre-trigger pulse will be sent to ADHWTSA to initiate an ADC acquisition using ADCx_SC1A configuration and store ADC conversion in ADCx_RA Register. Prior to the assertion of TPM1 channel 1 a pre-trigger pulse will be sent to ADHWTSB to initiate an ADC acquisition using ADCx_SC1Bconfiguration and store ADC conversion in ADCx_RB Register.
#0
1
ADC ADHWT trigger comes from a peripheral event selected by ADC0TRGSEL bits.ADC0PRETRGSEL bit will select the optional ADHWTSA or ADHWTSB select lines for choosing the ADCx_SC1x config and ADCx_Rx result regsiter to store the ADC conversion.
#1
ADC0PRETRGSEL
ADC0 Pretrigger Select
4
1
read-write
0
Pre-trigger ADHWTSA is selected, thus ADC0 will use ADC0_SC1A configuration for the next ADC conversion and store the result in ADC0_RA register.
#0
1
Pre-trigger ADHWTSB is selected, thus ADC0 will use ADC0_SC1B configuration for the next ADC conversion and store the result in ADC0_RB register.
#1
ADC0TRGSEL
ADC0 Trigger Select
0
4
read-write
0000
External trigger pin input (EXTRG_IN)
#0000
0001
CMP0 output
#0001
0100
PIT trigger 0
#0100
0101
PIT trigger 1
#0101
1000
TPM0 overflow
#1000
1001
TPM1 overflow
#1001
1010
TPM2 overflow
#1010
1100
RTC alarm
#1100
1101
RTC seconds
#1101
1110
LPTMR0 trigger
#1110
SRVCOP
Service COP
0x1104
32
write-only
n
0x0
0x0
SRVCOP
Service COP Register
0
8
write-only
UIDL
Unique Identification Register Low
0x1060
32
read-only
n
0x0
0x0
UID
Unique Identification
0
32
read-only
UIDMH
Unique Identification Register Mid-High
0x1058
32
read-only
n
0x0
0x0
UID
Unique Identification
0
16
read-only
UIDML
Unique Identification Register Mid Low
0x105C
32
read-only
n
0x0
0x0
UID
Unique Identification
0
32
read-only
SMC
System Mode Controller
SMC
0x0
0x0
0x4
registers
n
PMCTRL
Power Mode Control register
0x1
8
read-write
n
0x0
0x0
RUNM
Run Mode Control
5
2
read-write
00
Normal Run mode (RUN)
#00
10
Very-Low-Power Run mode (VLPR)
#10
STOPA
Stop Aborted
3
1
read-only
0
The previous stop mode entry was successful.
#0
1
The previous stop mode entry was aborted.
#1
STOPM
Stop Mode Control
0
3
read-write
000
Normal Stop (STOP)
#000
010
Very-Low-Power Stop (VLPS)
#010
011
Low-Leakage Stop (LLS)
#011
100
Very-Low-Leakage Stop (VLLSx)
#100
110
Reseved
#110
PMPROT
Power Mode Protection register
0x0
8
read-write
n
0x0
0x0
ALLS
Allow Low-Leakage Stop Mode
3
1
read-write
0
LLS is not allowed
#0
1
LLS is allowed
#1
AVLLS
Allow Very-Low-Leakage Stop Mode
1
1
read-write
0
Any VLLSx mode is not allowed
#0
1
Any VLLSx mode is allowed
#1
AVLP
Allow Very-Low-Power Modes
5
1
read-write
0
VLPR, VLPW, and VLPS are not allowed.
#0
1
VLPR, VLPW, and VLPS are allowed.
#1
PMSTAT
Power Mode Status register
0x3
8
read-only
n
0x0
0x0
PMSTAT
Power Mode Status
0
8
read-only
STOPCTRL
Stop Control Register
0x2
8
read-write
n
0x0
0x0
PORPO
POR Power Option
5
1
read-write
0
POR detect circuit is enabled in VLLS0
#0
1
POR detect circuit is disabled in VLLS0
#1
PSTOPO
Partial Stop Option
6
2
read-write
00
STOP - Normal Stop mode
#00
01
PSTOP1 - Partial Stop with both system and bus clocks disabled
#01
10
PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
#10
VLLSM
VLLS Mode Control
0
3
read-write
00
VLLS0
#000
01
VLLS1
#001
11
VLLS3
#011
SPI0
Serial Peripheral Interface
SPI
0x0
0x0
0x8
registers
n
SPI0
10
BR
SPI Baud Rate Register
0x1
8
read-write
n
0x0
0x0
SPPR
SPI Baud Rate Prescale Divisor
4
3
read-write
000
Baud rate prescaler divisor is 1.
#000
001
Baud rate prescaler divisor is 2.
#001
010
Baud rate prescaler divisor is 3.
#010
011
Baud rate prescaler divisor is 4.
#011
100
Baud rate prescaler divisor is 5.
#100
101
Baud rate prescaler divisor is 6.
#101
110
Baud rate prescaler divisor is 7.
#110
111
Baud rate prescaler divisor is 8.
#111
SPR
SPI Baud Rate Divisor
0
4
read-write
0000
Baud rate divisor is 2.
#0000
0001
Baud rate divisor is 4.
#0001
0010
Baud rate divisor is 8.
#0010
0011
Baud rate divisor is 16.
#0011
0100
Baud rate divisor is 32.
#0100
0101
Baud rate divisor is 64.
#0101
0110
Baud rate divisor is 128.
#0110
0111
Baud rate divisor is 256.
#0111
1000
Baud rate divisor is 512.
#1000
C1
SPI Control Register 1
0x3
8
read-write
n
0x0
0x0
CPHA
Clock Phase
2
1
read-write
0
First edge on SPSCK occurs at the middle of the first cycle of a data transfer.
#0
1
First edge on SPSCK occurs at the start of the first cycle of a data transfer.
#1
CPOL
Clock Polarity
3
1
read-write
0
Active-high SPI clock (idles low)
#0
1
Active-low SPI clock (idles high)
#1
LSBFE
LSB First (shifter direction)
0
1
read-write
0
SPI serial data transfers start with the most significant bit.
#0
1
SPI serial data transfers start with the least significant bit.
#1
MSTR
Master/Slave Mode Select
4
1
read-write
0
SPI module configured as a slave SPI device
#0
1
SPI module configured as a master SPI device
#1
SPE
SPI System Enable
6
1
read-write
0
SPI system inactive
#0
1
SPI system enabled
#1
SPIE
SPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO (when FIFO is supported and enabled)
7
1
read-write
0
Interrupts from SPRF and MODF are inhibited-use polling (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are disabled (when FIFOMODE is 1)
#0
1
Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are enabled (when FIFOMODE is 1)
#1
SPTIE
SPI Transmit Interrupt Enable
5
1
read-write
0
Interrupts from SPTEF inhibited (use polling)
#0
1
When SPTEF is 1, hardware interrupt requested
#1
SSOE
Slave Select Output Enable
1
1
read-write
0
When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.
#0
1
When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.
#1
C2
SPI Control Register 2
0x2
8
read-write
n
0x0
0x0
BIDIROE
Bidirectional Mode Output Enable
3
1
read-write
0
Output driver disabled so SPI data I/O pin acts as an input
#0
1
SPI I/O pin enabled as an output
#1
MODFEN
Master Mode-Fault Function Enable
4
1
read-write
0
Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
#0
1
Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
#1
RXDMAE
Receive DMA enable
2
1
read-write
0
DMA request for receive is disabled and interrupt from SPRF is allowed
#0
1
DMA request for receive is enabled and interrupt from SPRF is disabled
#1
SPC0
SPI Pin Control 0
0
1
read-write
0
SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.
#0
1
SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.
#1
SPIMODE
SPI 8-bit or 16-bit mode
6
1
read-write
0
8-bit SPI shift register, match register, and buffers
#0
1
16-bit SPI shift register, match register, and buffers
#1
SPISWAI
SPI Stop in Wait Mode
1
1
read-write
0
SPI clocks continue to operate in Wait mode.
#0
1
SPI clocks stop when the MCU enters Wait mode.
#1
SPMIE
SPI Match Interrupt Enable
7
1
read-write
0
Interrupts from SPMF inhibited (use polling)
#0
1
When SPMF is 1, requests a hardware interrupt
#1
TXDMAE
Transmit DMA enable
5
1
read-write
0
DMA request for transmit is disabled and interrupt from SPTEF is allowed
#0
1
DMA request for transmit is enabled and interrupt from SPTEF is disabled
#1
DH
SPI data register high
0x7
8
read-write
n
0x0
0x0
Bits
Data (high byte)
0
8
read-write
DL
SPI Data Register low
0x6
8
read-write
n
0x0
0x0
Bits
Data (low byte)
0
8
read-write
MH
SPI match register high
0x5
8
read-write
n
0x0
0x0
Bits
Hardware compare value (high byte)
0
8
read-write
ML
SPI Match Register low
0x4
8
read-write
n
0x0
0x0
Bits
Hardware compare value (low byte)
0
8
read-write
S
SPI Status Register
0x0
8
read-write
n
0x0
0x0
MODF
Master Mode Fault Flag
4
1
read-only
0
No mode fault error
#0
1
Mode fault error detected
#1
SPMF
SPI Match Flag
6
1
read-write
0
Value in the receive data buffer does not match the value in the MH:ML registers
#0
1
Value in the receive data buffer matches the value in the MH:ML registers
#1
SPRF
SPI Read Buffer Full Flag (when FIFO is not supported or not enabled) or SPI read FIFO FULL flag (when FIFO is supported and enabled)
7
1
read-only
0
No data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is not full (when FIFOMODE is 1)
#0
1
Data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is full (when FIFOMODE is 1)
#1
SPTEF
SPI Transmit Buffer Empty Flag (when FIFO is not supported or not enabled) or SPI transmit FIFO empty flag (when FIFO is supported and enabled)
5
1
read-only
0
SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when FIFOMODE is 1)
#0
1
SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when FIFOMODE is 1)
#1
SPI1
Serial Peripheral Interface
SPI
0x0
0x0
0xC
registers
n
SPI1
11
BR
SPI Baud Rate Register
0x1
8
read-write
n
0x0
0x0
SPPR
SPI Baud Rate Prescale Divisor
4
3
read-write
000
Baud rate prescaler divisor is 1.
#000
001
Baud rate prescaler divisor is 2.
#001
010
Baud rate prescaler divisor is 3.
#010
011
Baud rate prescaler divisor is 4.
#011
100
Baud rate prescaler divisor is 5.
#100
101
Baud rate prescaler divisor is 6.
#101
110
Baud rate prescaler divisor is 7.
#110
111
Baud rate prescaler divisor is 8.
#111
SPR
SPI Baud Rate Divisor
0
4
read-write
0000
Baud rate divisor is 2.
#0000
0001
Baud rate divisor is 4.
#0001
0010
Baud rate divisor is 8.
#0010
0011
Baud rate divisor is 16.
#0011
0100
Baud rate divisor is 32.
#0100
0101
Baud rate divisor is 64.
#0101
0110
Baud rate divisor is 128.
#0110
0111
Baud rate divisor is 256.
#0111
1000
Baud rate divisor is 512.
#1000
C1
SPI Control Register 1
0x3
8
read-write
n
0x0
0x0
CPHA
Clock Phase
2
1
read-write
0
First edge on SPSCK occurs at the middle of the first cycle of a data transfer.
#0
1
First edge on SPSCK occurs at the start of the first cycle of a data transfer.
#1
CPOL
Clock Polarity
3
1
read-write
0
Active-high SPI clock (idles low)
#0
1
Active-low SPI clock (idles high)
#1
LSBFE
LSB First (shifter direction)
0
1
read-write
0
SPI serial data transfers start with the most significant bit.
#0
1
SPI serial data transfers start with the least significant bit.
#1
MSTR
Master/Slave Mode Select
4
1
read-write
0
SPI module configured as a slave SPI device
#0
1
SPI module configured as a master SPI device
#1
SPE
SPI System Enable
6
1
read-write
0
SPI system inactive
#0
1
SPI system enabled
#1
SPIE
SPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO (when FIFO is supported and enabled)
7
1
read-write
0
Interrupts from SPRF and MODF are inhibited-use polling (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are disabled (when FIFOMODE is 1)
#0
1
Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are enabled (when FIFOMODE is 1)
#1
SPTIE
SPI Transmit Interrupt Enable
5
1
read-write
0
Interrupts from SPTEF inhibited (use polling)
#0
1
When SPTEF is 1, hardware interrupt requested
#1
SSOE
Slave Select Output Enable
1
1
read-write
0
When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.
#0
1
When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.
#1
C2
SPI Control Register 2
0x2
8
read-write
n
0x0
0x0
BIDIROE
Bidirectional Mode Output Enable
3
1
read-write
0
Output driver disabled so SPI data I/O pin acts as an input
#0
1
SPI I/O pin enabled as an output
#1
MODFEN
Master Mode-Fault Function Enable
4
1
read-write
0
Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
#0
1
Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
#1
RXDMAE
Receive DMA enable
2
1
read-write
0
DMA request for receive is disabled and interrupt from SPRF is allowed
#0
1
DMA request for receive is enabled and interrupt from SPRF is disabled
#1
SPC0
SPI Pin Control 0
0
1
read-write
0
SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.
#0
1
SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.
#1
SPIMODE
SPI 8-bit or 16-bit mode
6
1
read-write
0
8-bit SPI shift register, match register, and buffers
#0
1
16-bit SPI shift register, match register, and buffers
#1
SPISWAI
SPI Stop in Wait Mode
1
1
read-write
0
SPI clocks continue to operate in Wait mode.
#0
1
SPI clocks stop when the MCU enters Wait mode.
#1
SPMIE
SPI Match Interrupt Enable
7
1
read-write
0
Interrupts from SPMF inhibited (use polling)
#0
1
When SPMF is 1, requests a hardware interrupt
#1
TXDMAE
Transmit DMA enable
5
1
read-write
0
DMA request for transmit is disabled and interrupt from SPTEF is allowed
#0
1
DMA request for transmit is enabled and interrupt from SPTEF is disabled
#1
C3
SPI control register 3
0xB
8
read-write
n
0x0
0x0
FIFOMODE
FIFO mode enable
0
1
read-write
0
FIFO mode disabled
#0
1
FIFO mode enabled
#1
INTCLR
Interrupt clearing mechanism select
3
1
read-write
0
These interrupts are cleared when the corresponding flags are cleared depending on the state of the FIFOs
#0
1
These interrupts are cleared by writing the corresponding bits in the CI register
#1
RNFULLF_MARK
Receive FIFO nearly full watermark
4
1
read-write
0
RNFULLF is set when the receive FIFO has 48 bits or more
#0
1
RNFULLF is set when the receive FIFO has 32 bits or more
#1
RNFULLIEN
Receive FIFO nearly full interrupt enable
1
1
read-write
0
No interrupt upon RNFULLF being set
#0
1
Enable interrupts upon RNFULLF being set
#1
TNEAREF_MARK
Transmit FIFO nearly empty watermark
5
1
read-write
0
TNEAREF is set when the transmit FIFO has 16 bits or less
#0
1
TNEAREF is set when the transmit FIFO has 32 bits or less
#1
TNEARIEN
Transmit FIFO nearly empty interrupt enable
2
1
read-write
0
No interrupt upon TNEAREF being set
#0
1
Enable interrupts upon TNEAREF being set
#1
CI
SPI clear interrupt register
0xA
8
read-write
n
0x0
0x0
RNFULLFCI
Receive FIFO nearly full flag clear interrupt
2
1
read-write
RXFERR
Receive FIFO error flag
6
1
read-only
0
No receive FIFO error occurred
#0
1
A receive FIFO error occurred
#1
RXFOF
Receive FIFO overflow flag
4
1
read-only
0
Receive FIFO overflow condition has not occurred
#0
1
Receive FIFO overflow condition occurred
#1
SPRFCI
Receive FIFO full flag clear interrupt
0
1
read-write
SPTEFCI
Transmit FIFO empty flag clear interrupt
1
1
read-write
TNEAREFCI
Transmit FIFO nearly empty flag clear interrupt
3
1
read-write
TXFERR
Transmit FIFO error flag
7
1
read-only
0
No transmit FIFO error occurred
#0
1
A transmit FIFO error occurred
#1
TXFOF
Transmit FIFO overflow flag
5
1
read-only
0
Transmit FIFO overflow condition has not occurred
#0
1
Transmit FIFO overflow condition occurred
#1
DH
SPI data register high
0x7
8
read-write
n
0x0
0x0
Bits
Data (high byte)
0
8
read-write
DL
SPI Data Register low
0x6
8
read-write
n
0x0
0x0
Bits
Data (low byte)
0
8
read-write
MH
SPI match register high
0x5
8
read-write
n
0x0
0x0
Bits
Hardware compare value (high byte)
0
8
read-write
ML
SPI Match Register low
0x4
8
read-write
n
0x0
0x0
Bits
Hardware compare value (low byte)
0
8
read-write
S
SPI Status Register
0x0
8
read-write
n
0x0
0x0
MODF
Master Mode Fault Flag
4
1
read-only
0
No mode fault error
#0
1
Mode fault error detected
#1
RFIFOEF
SPI read FIFO empty flag
0
1
read-only
0
Read FIFO has data. Reads of the DH:DL registers in 16-bit mode or the DL register in 8-bit mode will empty the read FIFO.
#0
1
Read FIFO is empty.
#1
RNFULLF
Receive FIFO nearly full flag
3
1
read-only
0
Receive FIFO has received less than 48 bits (when C3[RNFULLF_MARK] is 0) or less than 32 bits (when C3[RNFULLF_MARK] is 1)
#0
1
Receive FIFO has received data of an amount equal to or greater than 48 bits (when C3[RNFULLF_MARK] is 0) or 32 bits (when C3[RNFULLF_MARK] is 1)
#1
SPMF
SPI Match Flag
6
1
read-write
0
Value in the receive data buffer does not match the value in the MH:ML registers
#0
1
Value in the receive data buffer matches the value in the MH:ML registers
#1
SPRF
SPI Read Buffer Full Flag (when FIFO is not supported or not enabled) or SPI read FIFO FULL flag (when FIFO is supported and enabled)
7
1
read-only
0
No data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is not full (when FIFOMODE is 1)
#0
1
Data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is full (when FIFOMODE is 1)
#1
SPTEF
SPI Transmit Buffer Empty Flag (when FIFO is not supported or not enabled) or SPI transmit FIFO empty flag (when FIFO is supported and enabled)
5
1
read-only
0
SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when FIFOMODE is 1)
#0
1
SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when FIFOMODE is 1)
#1
TNEAREF
Transmit FIFO nearly empty flag
2
1
read-only
0
Transmit FIFO has more than 16 bits (when C3[TNEAREF_MARK] is 0) or more than 32 bits (when C3[TNEAREF_MARK] is 1) remaining to transmit
#0
1
Transmit FIFO has an amount of data equal to or less than 16 bits (when C3[TNEAREF_MARK] is 0) or 32 bits (when C3[TNEAREF_MARK] is 1) remaining to transmit
#1
TXFULLF
Transmit FIFO full flag
1
1
read-only
0
Transmit FIFO has less than 8 bytes
#0
1
Transmit FIFO has 8 bytes of data
#1
SystemControl
System Control Block
SystemControl
0x0
0x8
0xD2C
registers
n
SCB_ACTLR
Auxiliary Control Register,
0x8
32
read-only
n
0x0
0x0
SCB_AIRCR
Application Interrupt and Reset Control Register
0xD0C
32
read-write
n
0x0
0x0
ENDIANNESS
Data endianness bit
15
1
read-only
0
Little-endian
#0
1
Big-endian
#1
SYSRESETREQ
System reset request
2
1
write-only
0
no system reset request
#0
1
asserts a signal to the outer system that requests a reset
#1
VECTCLRACTIVE
Reserved for Debug use
1
1
write-only
VECTKEY
Register key
16
16
read-write
SCB_CCR
Configuration and Control Register
0xD14
32
read-only
n
0x0
0x0
STKALIGN
Indicates stack alignment on exception entry
9
1
read-only
UNALIGN_TRP
Always reads as one, indicates that all unaligned accesses generate a HardFault
3
1
read-only
SCB_CPUID
CPUID Base Register
0xD00
32
read-only
n
0x0
0x0
ARCHITECTURE
Indicates the architecture
16
4
read-only
IMPLEMENTER
Implementer code
24
8
read-only
PARTNO
Indicates part number
4
12
read-only
REVISION
Minor revision number m in the rnpm revision status
0
4
read-only
VARIANT
Major revision number n in the npm revision status
20
4
read-only
SCB_DFSR
Debug Fault Status Register
0xD30
32
read-write
n
0x0
0x0
BKPT
no description available
1
1
read-write
0
No current breakpoint debug event
#0
1
At least one current breakpoint debug event
#1
DWTTRAP
no description available
2
1
read-write
0
No current debug events generated by the DWT
#0
1
At least one current debug event generated by the DWT
#1
EXTERNAL
no description available
4
1
read-write
0
No EDBGRQ debug event
#0
1
EDBGRQ debug event
#1
HALTED
no description available
0
1
read-write
0
No active halt request debug event
#0
1
Halt request debug event active
#1
VCATCH
no description available
3
1
read-write
0
No Vector catch triggered
#0
1
Vector catch triggered
#1
SCB_ICSR
Interrupt Control and State Register
0xD04
32
read-write
n
0x0
0x0
NMIPENDSET
NMI set-pending bit
31
1
read-write
0
write: no effect; read: NMI exception is not pending
#0
1
write: changes NMI exception state to pending; read: NMI exception is pending
#1
PENDSTCLR
SysTick exception clear-pending bit
25
1
write-only
0
no effect
#0
1
removes the pending state from the SysTick exception
#1
PENDSTSET
SysTick exception set-pending bit
26
1
read-write
0
write: no effect; read: SysTick exception is not pending
#0
1
write: changes SysTick exception state to pending; read: SysTick exception is pending
#1
PENDSVCLR
PendSV clear-pending bit
27
1
write-only
0
no effect
#0
1
removes the pending state from the PendSV exception
#1
PENDSVSET
PendSV set-pending bit
28
1
read-write
0
write: no effect; read: PendSV exception is not pending
#0
1
write: changes PendSV exception state to pending; read: PendSV exception is pending
#1
VECTPENDING
Exception number of the highest priority pending enabled exception
12
6
read-only
SCB_SCR
System Control Register
0xD10
32
read-write
n
0x0
0x0
SEVONPEND
Send Event on Pending bit
4
1
read-write
0
only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
#0
1
enabled events and all interrupts, including disabled interrupts, can wakeup the processor
#1
SLEEPDEEP
Controls whether the processor uses sleep or deep sleep as its low power mode
2
1
read-write
0
sleep
#0
1
deep sleep
#1
SLEEPONEXIT
Indicates sleep-on-exit when returning from Handler mode to Thread mode
1
1
read-write
0
do not sleep when returning to Thread mode
#0
1
enter sleep, or deep sleep, on return from an ISR
#1
SCB_SHCSR
System Handler Control and State Register
0xD24
32
read-write
n
0x0
0x0
SVCALLPENDED
no description available
15
1
read-write
0
exception is not pending
#0
1
exception is pending
#1
SCB_SHPR2
System Handler Priority Register 2
0xD1C
32
read-write
n
0x0
0x0
PRI_11
Priority of system handler 11, SVCall
30
2
read-write
SCB_SHPR3
System Handler Priority Register 3
0xD20
32
read-write
n
0x0
0x0
PRI_14
Priority of system handler 14, PendSV
22
2
read-write
PRI_15
Priority of system handler 15, SysTick exception
30
2
read-write
SCB_VTOR
Vector Table Offset Register
0xD08
32
read-write
n
0x0
0x0
TBLOFF
Vector table base offset
7
25
read-write
SysTick
System timer
SysTick
0x0
0x0
0x10
registers
n
SYST_CALIB
SysTick Calibration Value Register
0xC
32
read-only
n
0x0
0x0
NOREF
no description available
31
1
read-only
0
The reference clock is provided
#0
1
The reference clock is not provided
#1
SKEW
no description available
30
1
read-only
0
10ms calibration value is exact
#0
1
10ms calibration value is inexact, because of the clock frequency
#1
TENMS
Reload value to use for 10ms timing
0
24
read-only
SYST_CSR
SysTick Control and Status Register
0x0
32
read-write
n
0x0
0x0
CLKSOURCE
no description available
2
1
read-write
0
external clock
#0
1
processor clock
#1
COUNTFLAG
no description available
16
1
read-write
ENABLE
no description available
0
1
read-write
0
counter disabled
#0
1
counter enabled
#1
TICKINT
no description available
1
1
read-write
0
counting down to 0 does not assert the SysTick exception request
#0
1
counting down to 0 asserts the SysTick exception request
#1
SYST_CVR
SysTick Current Value Register
0x8
32
read-write
n
0x0
0x0
CURRENT
Current value at the time the register is accessed
0
24
read-write
SYST_RVR
SysTick Reload Value Register
0x4
32
read-write
n
0x0
0x0
RELOAD
Value to load into the SysTick Current Value Register when the counter reaches 0
0
24
read-write
TPM0
Timer/PWM Module
TPM
0x0
0x0
0x88
registers
n
TPM0
17
C0SC
Channel (n) Status and Control
0x18
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts.
#0
1
Enable channel interrupts.
#1
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
C0V
Channel (n) Value
0x20
32
read-write
n
0x0
0x0
VAL
Channel Value
0
16
read-write
C1SC
Channel (n) Status and Control
0x2C
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts.
#0
1
Enable channel interrupts.
#1
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
C1V
Channel (n) Value
0x38
32
read-write
n
0x0
0x0
VAL
Channel Value
0
16
read-write
C2SC
Channel (n) Status and Control
0x48
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts.
#0
1
Enable channel interrupts.
#1
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
C2V
Channel (n) Value
0x58
32
read-write
n
0x0
0x0
VAL
Channel Value
0
16
read-write
C3SC
Channel (n) Status and Control
0x6C
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts.
#0
1
Enable channel interrupts.
#1
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
C3V
Channel (n) Value
0x80
32
read-write
n
0x0
0x0
VAL
Channel Value
0
16
read-write
C4SC
Channel (n) Status and Control
0x98
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts.
#0
1
Enable channel interrupts.
#1
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
C4V
Channel (n) Value
0xB0
32
read-write
n
0x0
0x0
VAL
Channel Value
0
16
read-write
C5SC
Channel (n) Status and Control
0xCC
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts.
#0
1
Enable channel interrupts.
#1
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
C5V
Channel (n) Value
0xE8
32
read-write
n
0x0
0x0
VAL
Channel Value
0
16
read-write
CNT
Counter
0x4
32
read-write
n
0x0
0x0
COUNT
Counter value
0
16
read-write
CONF
Configuration
0x84
32
read-write
n
0x0
0x0
CPOT
Counter Pause On Trigger
19
1
read-write
CROT
Counter Reload On Trigger
18
1
read-write
0
Counter is not reloaded due to a rising edge on the selected input trigger
#0
1
Counter is reloaded when a rising edge is detected on the selected input trigger
#1
CSOO
Counter Stop On Overflow
17
1
read-write
0
TPM counter continues incrementing or decrementing after overflow
#0
1
TPM counter stops incrementing or decrementing after overflow.
#1
CSOT
Counter Start on Trigger
16
1
read-write
0
TPM counter starts to increment immediately, once it is enabled.
#0
1
TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.
#1
DBGMODE
Debug Mode
6
2
read-write
00
TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.
#00
11
TPM counter continues in debug mode.
#11
DOZEEN
Doze Enable
5
1
read-write
0
Internal TPM counter continues in Doze mode.
#0
1
Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.
#1
GTBEEN
Global time base enable
9
1
read-write
0
All channels use the internally generated TPM counter as their timebase
#0
1
All channels use an externally generated global timebase as their timebase
#1
GTBSYNC
Global Time Base Synchronization
8
1
read-write
0
Global timebase synchronization disabled.
#0
1
Global timebase synchronization enabled.
#1
TRGPOL
Trigger Polarity
22
1
read-write
0
Trigger is active high.
#0
1
Trigger is active low.
#1
TRGSEL
Trigger Select
24
4
read-write
0001
Channel 0 pin input capture
#0001
0010
Channel 1 pin input capture
#0010
0011
Channel 0 or Channel 1 pin input capture
#0011
0100
Channel 2 pin input capture
#0100
0101
Channel 0 or Channel 2 pin input capture
#0101
0110
Channel 1 or Channel 2 pin input capture
#0110
0111
Channel 0 or Channel 1 or Channel 2 pin input capture
#0111
1000
Channel 3 pin input capture
#1000
1001
Channel 0 or Channel 3 pin input capture
#1001
1010
Channel 1 or Channel 3 pin input capture
#1010
1011
Channel 0 or Channel 1 or Channel 3 pin input capture
#1011
1100
Channel 2 or Channel 3 pin input capture
#1100
1101
Channel 0 or Channel 2 or Channel 3 pin input capture
#1101
1110
Channel 1 or Channel 2 or Channel 3 pin input capture
#1110
1111
Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture
#1111
TRGSRC
Trigger Source
23
1
read-write
0
Trigger source selected by TRGSEL is external.
#0
1
Trigger source selected by TRGSEL is internal (channel pin input capture).
#1
MOD
Modulo
0x8
32
read-write
n
0x0
0x0
MOD
Modulo value
0
16
read-write
POL
Channel Polarity
0x70
32
read-write
n
0x0
0x0
POL0
Channel 0 Polarity
0
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL1
Channel 1 Polarity
1
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL2
Channel 2 Polarity
2
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL3
Channel 3 Polarity
3
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL4
Channel 4 Polarity
4
1
read-write
0
The channel polarity is active high
#0
1
The channel polarity is active low.
#1
POL5
Channel 5 Polarity
5
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
SC
Status and Control
0x0
32
read-write
n
0x0
0x0
CMOD
Clock Mode Selection
3
2
read-write
00
TPM counter is disabled
#00
01
TPM counter increments on every TPM counter clock
#01
10
TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock
#10
CPWMS
Center-Aligned PWM Select
5
1
read-write
0
TPM counter operates in up counting mode.
#0
1
TPM counter operates in up-down counting mode.
#1
DMA
DMA Enable
8
1
read-write
0
Disables DMA transfers.
#0
1
Enables DMA transfers.
#1
PS
Prescale Factor Selection
0
3
read-write
000
Divide by 1
#000
001
Divide by 2
#001
010
Divide by 4
#010
011
Divide by 8
#011
100
Divide by 16
#100
101
Divide by 32
#101
110
Divide by 64
#110
111
Divide by 128
#111
TOF
Timer Overflow Flag
7
1
read-write
0
TPM counter has not overflowed.
#0
1
TPM counter has overflowed.
#1
TOIE
Timer Overflow Interrupt Enable
6
1
read-write
0
Disable TOF interrupts. Use software polling or DMA request.
#0
1
Enable TOF interrupts. An interrupt is generated when TOF equals one.
#1
STATUS
Capture and Compare Status
0x50
32
read-write
n
0x0
0x0
CH0F
Channel 0 Flag
0
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH1F
Channel 1 Flag
1
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH2F
Channel 2 Flag
2
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH3F
Channel 3 Flag
3
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH4F
Channel 4 Flag
4
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH5F
Channel 5 Flag
5
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
TOF
Timer Overflow Flag
8
1
read-write
0
TPM counter has not overflowed.
#0
1
TPM counter has overflowed.
#1
TPM1
Timer/PWM Module
TPM
0x0
0x0
0x88
registers
n
TPM1
18
C0SC
Channel (n) Status and Control
0x18
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts.
#0
1
Enable channel interrupts.
#1
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
C0V
Channel (n) Value
0x20
32
read-write
n
0x0
0x0
VAL
Channel Value
0
16
read-write
C1SC
Channel (n) Status and Control
0x2C
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts.
#0
1
Enable channel interrupts.
#1
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
C1V
Channel (n) Value
0x38
32
read-write
n
0x0
0x0
VAL
Channel Value
0
16
read-write
CNT
Counter
0x4
32
read-write
n
0x0
0x0
COUNT
Counter value
0
16
read-write
CONF
Configuration
0x84
32
read-write
n
0x0
0x0
CPOT
Counter Pause On Trigger
19
1
read-write
CROT
Counter Reload On Trigger
18
1
read-write
0
Counter is not reloaded due to a rising edge on the selected input trigger
#0
1
Counter is reloaded when a rising edge is detected on the selected input trigger
#1
CSOO
Counter Stop On Overflow
17
1
read-write
0
TPM counter continues incrementing or decrementing after overflow
#0
1
TPM counter stops incrementing or decrementing after overflow.
#1
CSOT
Counter Start on Trigger
16
1
read-write
0
TPM counter starts to increment immediately, once it is enabled.
#0
1
TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.
#1
DBGMODE
Debug Mode
6
2
read-write
00
TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.
#00
11
TPM counter continues in debug mode.
#11
DOZEEN
Doze Enable
5
1
read-write
0
Internal TPM counter continues in Doze mode.
#0
1
Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.
#1
GTBEEN
Global time base enable
9
1
read-write
0
All channels use the internally generated TPM counter as their timebase
#0
1
All channels use an externally generated global timebase as their timebase
#1
GTBSYNC
Global Time Base Synchronization
8
1
read-write
0
Global timebase synchronization disabled.
#0
1
Global timebase synchronization enabled.
#1
TRGPOL
Trigger Polarity
22
1
read-write
0
Trigger is active high.
#0
1
Trigger is active low.
#1
TRGSEL
Trigger Select
24
4
read-write
0001
Channel 0 pin input capture
#0001
0010
Channel 1 pin input capture
#0010
0011
Channel 0 or Channel 1 pin input capture
#0011
0100
Channel 2 pin input capture
#0100
0101
Channel 0 or Channel 2 pin input capture
#0101
0110
Channel 1 or Channel 2 pin input capture
#0110
0111
Channel 0 or Channel 1 or Channel 2 pin input capture
#0111
1000
Channel 3 pin input capture
#1000
1001
Channel 0 or Channel 3 pin input capture
#1001
1010
Channel 1 or Channel 3 pin input capture
#1010
1011
Channel 0 or Channel 1 or Channel 3 pin input capture
#1011
1100
Channel 2 or Channel 3 pin input capture
#1100
1101
Channel 0 or Channel 2 or Channel 3 pin input capture
#1101
1110
Channel 1 or Channel 2 or Channel 3 pin input capture
#1110
1111
Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture
#1111
TRGSRC
Trigger Source
23
1
read-write
0
Trigger source selected by TRGSEL is external.
#0
1
Trigger source selected by TRGSEL is internal (channel pin input capture).
#1
MOD
Modulo
0x8
32
read-write
n
0x0
0x0
MOD
Modulo value
0
16
read-write
POL
Channel Polarity
0x70
32
read-write
n
0x0
0x0
POL0
Channel 0 Polarity
0
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL1
Channel 1 Polarity
1
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL2
Channel 2 Polarity
2
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL3
Channel 3 Polarity
3
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL4
Channel 4 Polarity
4
1
read-write
0
The channel polarity is active high
#0
1
The channel polarity is active low.
#1
POL5
Channel 5 Polarity
5
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
SC
Status and Control
0x0
32
read-write
n
0x0
0x0
CMOD
Clock Mode Selection
3
2
read-write
00
TPM counter is disabled
#00
01
TPM counter increments on every TPM counter clock
#01
10
TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock
#10
CPWMS
Center-Aligned PWM Select
5
1
read-write
0
TPM counter operates in up counting mode.
#0
1
TPM counter operates in up-down counting mode.
#1
DMA
DMA Enable
8
1
read-write
0
Disables DMA transfers.
#0
1
Enables DMA transfers.
#1
PS
Prescale Factor Selection
0
3
read-write
000
Divide by 1
#000
001
Divide by 2
#001
010
Divide by 4
#010
011
Divide by 8
#011
100
Divide by 16
#100
101
Divide by 32
#101
110
Divide by 64
#110
111
Divide by 128
#111
TOF
Timer Overflow Flag
7
1
read-write
0
TPM counter has not overflowed.
#0
1
TPM counter has overflowed.
#1
TOIE
Timer Overflow Interrupt Enable
6
1
read-write
0
Disable TOF interrupts. Use software polling or DMA request.
#0
1
Enable TOF interrupts. An interrupt is generated when TOF equals one.
#1
STATUS
Capture and Compare Status
0x50
32
read-write
n
0x0
0x0
CH0F
Channel 0 Flag
0
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH1F
Channel 1 Flag
1
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH2F
Channel 2 Flag
2
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH3F
Channel 3 Flag
3
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH4F
Channel 4 Flag
4
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH5F
Channel 5 Flag
5
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
TOF
Timer Overflow Flag
8
1
read-write
0
TPM counter has not overflowed.
#0
1
TPM counter has overflowed.
#1
TPM2
Timer/PWM Module
TPM
0x0
0x0
0x88
registers
n
TPM2
19
C0SC
Channel (n) Status and Control
0x18
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts.
#0
1
Enable channel interrupts.
#1
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
C0V
Channel (n) Value
0x20
32
read-write
n
0x0
0x0
VAL
Channel Value
0
16
read-write
C1SC
Channel (n) Status and Control
0x2C
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts.
#0
1
Enable channel interrupts.
#1
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
C1V
Channel (n) Value
0x38
32
read-write
n
0x0
0x0
VAL
Channel Value
0
16
read-write
CNT
Counter
0x4
32
read-write
n
0x0
0x0
COUNT
Counter value
0
16
read-write
CONF
Configuration
0x84
32
read-write
n
0x0
0x0
CPOT
Counter Pause On Trigger
19
1
read-write
CROT
Counter Reload On Trigger
18
1
read-write
0
Counter is not reloaded due to a rising edge on the selected input trigger
#0
1
Counter is reloaded when a rising edge is detected on the selected input trigger
#1
CSOO
Counter Stop On Overflow
17
1
read-write
0
TPM counter continues incrementing or decrementing after overflow
#0
1
TPM counter stops incrementing or decrementing after overflow.
#1
CSOT
Counter Start on Trigger
16
1
read-write
0
TPM counter starts to increment immediately, once it is enabled.
#0
1
TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.
#1
DBGMODE
Debug Mode
6
2
read-write
00
TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.
#00
11
TPM counter continues in debug mode.
#11
DOZEEN
Doze Enable
5
1
read-write
0
Internal TPM counter continues in Doze mode.
#0
1
Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.
#1
GTBEEN
Global time base enable
9
1
read-write
0
All channels use the internally generated TPM counter as their timebase
#0
1
All channels use an externally generated global timebase as their timebase
#1
GTBSYNC
Global Time Base Synchronization
8
1
read-write
0
Global timebase synchronization disabled.
#0
1
Global timebase synchronization enabled.
#1
TRGPOL
Trigger Polarity
22
1
read-write
0
Trigger is active high.
#0
1
Trigger is active low.
#1
TRGSEL
Trigger Select
24
4
read-write
0001
Channel 0 pin input capture
#0001
0010
Channel 1 pin input capture
#0010
0011
Channel 0 or Channel 1 pin input capture
#0011
0100
Channel 2 pin input capture
#0100
0101
Channel 0 or Channel 2 pin input capture
#0101
0110
Channel 1 or Channel 2 pin input capture
#0110
0111
Channel 0 or Channel 1 or Channel 2 pin input capture
#0111
1000
Channel 3 pin input capture
#1000
1001
Channel 0 or Channel 3 pin input capture
#1001
1010
Channel 1 or Channel 3 pin input capture
#1010
1011
Channel 0 or Channel 1 or Channel 3 pin input capture
#1011
1100
Channel 2 or Channel 3 pin input capture
#1100
1101
Channel 0 or Channel 2 or Channel 3 pin input capture
#1101
1110
Channel 1 or Channel 2 or Channel 3 pin input capture
#1110
1111
Channel 0 or Channel 1 or Channel 2 or Channel 3 pin input capture
#1111
TRGSRC
Trigger Source
23
1
read-write
0
Trigger source selected by TRGSEL is external.
#0
1
Trigger source selected by TRGSEL is internal (channel pin input capture).
#1
MOD
Modulo
0x8
32
read-write
n
0x0
0x0
MOD
Modulo value
0
16
read-write
POL
Channel Polarity
0x70
32
read-write
n
0x0
0x0
POL0
Channel 0 Polarity
0
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL1
Channel 1 Polarity
1
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL2
Channel 2 Polarity
2
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL3
Channel 3 Polarity
3
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL4
Channel 4 Polarity
4
1
read-write
0
The channel polarity is active high
#0
1
The channel polarity is active low.
#1
POL5
Channel 5 Polarity
5
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
SC
Status and Control
0x0
32
read-write
n
0x0
0x0
CMOD
Clock Mode Selection
3
2
read-write
00
TPM counter is disabled
#00
01
TPM counter increments on every TPM counter clock
#01
10
TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock
#10
CPWMS
Center-Aligned PWM Select
5
1
read-write
0
TPM counter operates in up counting mode.
#0
1
TPM counter operates in up-down counting mode.
#1
DMA
DMA Enable
8
1
read-write
0
Disables DMA transfers.
#0
1
Enables DMA transfers.
#1
PS
Prescale Factor Selection
0
3
read-write
000
Divide by 1
#000
001
Divide by 2
#001
010
Divide by 4
#010
011
Divide by 8
#011
100
Divide by 16
#100
101
Divide by 32
#101
110
Divide by 64
#110
111
Divide by 128
#111
TOF
Timer Overflow Flag
7
1
read-write
0
TPM counter has not overflowed.
#0
1
TPM counter has overflowed.
#1
TOIE
Timer Overflow Interrupt Enable
6
1
read-write
0
Disable TOF interrupts. Use software polling or DMA request.
#0
1
Enable TOF interrupts. An interrupt is generated when TOF equals one.
#1
STATUS
Capture and Compare Status
0x50
32
read-write
n
0x0
0x0
CH0F
Channel 0 Flag
0
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH1F
Channel 1 Flag
1
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH2F
Channel 2 Flag
2
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH3F
Channel 3 Flag
3
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH4F
Channel 4 Flag
4
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH5F
Channel 5 Flag
5
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
TOF
Timer Overflow Flag
8
1
read-write
0
TPM counter has not overflowed.
#0
1
TPM counter has overflowed.
#1
UART2
Serial Communication Interface
UART2
0x0
0x0
0x40
registers
n
UART2_FLEXIO
14
AP7816A_T0
UART 7816 ATR Duration Timer Register A
0x3A
8
read-write
n
0x0
0x0
ADTI_H
ATR Duration Time Integer High (C7816[TTYPE] = 0)
0
8
read-write
AP7816B_T0
UART 7816 ATR Duration Timer Register B
0x3B
8
read-write
n
0x0
0x0
ADTI_L
ATR Duration Time Integer Low (C7816[TTYPE] = 0)
0
8
read-write
BDH
UART Baud Rate Registers: High
0x0
8
read-write
n
0x0
0x0
RXEDGIE
RxD Input Active Edge Interrupt Enable
6
1
read-write
0
Hardware interrupts from RXEDGIF disabled using polling.
#0
1
RXEDGIF interrupt request enabled.
#1
SBR
UART Baud Rate Bits
0
5
read-write
BDL
UART Baud Rate Registers: Low
0x1
8
read-write
n
0x0
0x0
SBR
UART Baud Rate Bits
0
8
read-write
C1
UART Control Register 1
0x2
8
read-write
n
0x0
0x0
ILT
Idle Line Type Select
2
1
read-write
0
Idle character bit count starts after start bit.
#0
1
Idle character bit count starts after stop bit.
#1
LOOPS
Loop Mode Select
7
1
read-write
0
Normal operation.
#0
1
Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.
#1
M
9-bit or 8-bit Mode Select
4
1
read-write
0
Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
#0
1
Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
#1
PE
Parity Enable
1
1
read-write
0
Parity function disabled.
#0
1
Parity function enabled.
#1
PT
Parity Type
0
1
read-write
0
Even parity.
#0
1
Odd parity.
#1
RSRC
Receiver Source Select
5
1
read-write
0
Selects internal loop back mode. The receiver input is internally connected to transmitter output.
#0
1
Single wire UART mode where the receiver input is connected to the transmit pin input signal.
#1
WAKE
Receiver Wakeup Method Select
3
1
read-write
0
Idle line wakeup.
#0
1
Address mark wakeup.
#1
C2
UART Control Register 2
0x3
8
read-write
n
0x0
0x0
ILIE
Idle Line Interrupt Enable
4
1
read-write
0
IDLE interrupt requests disabled.
#0
1
IDLE interrupt requests enabled.
#1
RE
Receiver Enable
2
1
read-write
0
Receiver off.
#0
1
Receiver on.
#1
RIE
Receiver Full Interrupt or DMA Transfer Enable
5
1
read-write
0
RDRF interrupt and DMA transfer requests disabled.
#0
1
RDRF interrupt or DMA transfer requests enabled.
#1
RWU
Receiver Wakeup Control
1
1
read-write
0
Normal operation.
#0
1
RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.
#1
SBK
Send Break
0
1
read-write
0
Normal transmitter operation.
#0
1
Queue break characters to be sent.
#1
TCIE
Transmission Complete Interrupt Enable
6
1
read-write
0
TC interrupt requests disabled.
#0
1
TC interrupt requests enabled.
#1
TE
Transmitter Enable
3
1
read-write
0
Transmitter off.
#0
1
Transmitter on.
#1
TIE
Transmitter Interrupt or DMA Transfer Enable.
7
1
read-write
0
TDRE interrupt and DMA transfer requests disabled.
#0
1
TDRE interrupt or DMA transfer requests enabled.
#1
C3
UART Control Register 3
0x6
8
read-write
n
0x0
0x0
FEIE
Framing Error Interrupt Enable
1
1
read-write
0
FE interrupt requests are disabled.
#0
1
FE interrupt requests are enabled.
#1
NEIE
Noise Error Interrupt Enable
2
1
read-write
0
NF interrupt requests are disabled.
#0
1
NF interrupt requests are enabled.
#1
ORIE
Overrun Error Interrupt Enable
3
1
read-write
0
OR interrupts are disabled.
#0
1
OR interrupt requests are enabled.
#1
PEIE
Parity Error Interrupt Enable
0
1
read-write
0
PF interrupt requests are disabled.
#0
1
PF interrupt requests are enabled.
#1
R8
Received Bit 8
7
1
read-only
T8
Transmit Bit 8
6
1
read-write
TXDIR
Transmitter Pin Data Direction in Single-Wire mode
5
1
read-write
0
TXD pin is an input in single wire mode.
#0
1
TXD pin is an output in single wire mode.
#1
TXINV
Transmit Data Inversion.
4
1
read-write
0
Transmit data is not inverted.
#0
1
Transmit data is inverted.
#1
C4
UART Control Register 4
0xA
8
read-write
n
0x0
0x0
BRFA
Baud Rate Fine Adjust
0
5
read-write
M10
10-bit Mode select
5
1
read-write
0
The parity bit is the ninth bit in the serial transmission.
#0
1
The parity bit is the tenth bit in the serial transmission.
#1
MAEN1
Match Address Mode Enable 1
7
1
read-write
0
All data received is transferred to the data buffer if MAEN2 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
MAEN2
Match Address Mode Enable 2
6
1
read-write
0
All data received is transferred to the data buffer if MAEN1 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
C5
UART Control Register 5
0xB
8
read-write
n
0x0
0x0
RDMAS
Receiver Full DMA Select
5
1
read-write
0
If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.
#1
TDMAS
Transmitter DMA Select
7
1
read-write
0
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
#0
1
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
#1
C7816
UART 7816 Control Register
0x18
8
read-write
n
0x0
0x0
ANACK
Generate NACK on Error
3
1
read-write
0
No NACK is automatically generated.
#0
1
A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected.
#1
INIT
Detect Initial Character
2
1
read-write
0
Normal operating mode. Receiver does not seek to identify initial character.
#0
1
Receiver searches for initial character.
#1
ISO_7816E
ISO-7816 Functionality Enabled
0
1
read-write
0
ISO-7816 functionality is turned off/not enabled.
#0
1
ISO-7816 functionality is turned on/enabled.
#1
ONACK
Generate NACK on Overflow
4
1
read-write
0
The received data does not generate a NACK when the receipt of the data results in an overflow event.
#0
1
If the receiver buffer overflows, a NACK is automatically sent on a received character.
#1
TTYPE
Transfer Type
1
1
read-write
0
T = 0 per the ISO-7816 specification.
#0
1
T = 1 per the ISO-7816 specification.
#1
D
UART Data Register
0x7
8
read-write
n
0x0
0x0
RT
Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register
0
8
read-write
ET7816
UART 7816 Error Threshold Register
0x1E
8
read-write
n
0x0
0x0
RXTHRESHOLD
Receive NACK Threshold
0
4
read-write
TXTHRESHOLD
Transmit NACK Threshold
4
4
read-write
0
TXT asserts on the first NACK that is received.
#0000
1
TXT asserts on the second NACK that is received.
#0001
IE7816
UART 7816 Interrupt Enable Register
0x19
8
read-write
n
0x0
0x0
ADTE
ATR Duration Timer Interrupt Enable
3
1
read-write
0
The assertion of IS7816[ADT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[ADT] results in the generation of an interrupt.
#1
BWTE
Block Wait Timer Interrupt Enable
5
1
read-write
0
The assertion of IS7816[BWT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[BWT] results in the generation of an interrupt.
#1
CWTE
Character Wait Timer Interrupt Enable
6
1
read-write
0
The assertion of IS7816[CWT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[CWT] results in the generation of an interrupt.
#1
GTVE
Guard Timer Violated Interrupt Enable
2
1
read-write
0
The assertion of IS7816[GTV] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[GTV] results in the generation of an interrupt.
#1
INITDE
Initial Character Detected Interrupt Enable
4
1
read-write
0
The assertion of IS7816[INITD] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[INITD] results in the generation of an interrupt.
#1
RXTE
Receive Threshold Exceeded Interrupt Enable
0
1
read-write
0
The assertion of IS7816[RXT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[RXT] results in the generation of an interrupt.
#1
TXTE
Transmit Threshold Exceeded Interrupt Enable
1
1
read-write
0
The assertion of IS7816[TXT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[TXT] results in the generation of an interrupt.
#1
WTE
Wait Timer Interrupt Enable
7
1
read-write
0
The assertion of IS7816[WT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[WT] results in the generation of an interrupt.
#1
IS7816
UART 7816 Interrupt Status Register
0x1A
8
read-write
n
0x0
0x0
ADT
ATR Duration Time Interrupt
3
1
read-write
0
ATR Duration time (ADT) has not been violated.
#0
1
ATR Duration time (ADT) has been violated.
#1
BWT
Block Wait Timer Interrupt
5
1
read-write
0
Block wait time (BWT) has not been violated.
#0
1
Block wait time (BWT) has been violated.
#1
CWT
Character Wait Timer Interrupt
6
1
read-write
0
Character wait time (CWT) has not been violated.
#0
1
Character wait time (CWT) has been violated.
#1
GTV
Guard Timer Violated Interrupt
2
1
read-write
0
A guard time (GT, CGT, or BGT) has not been violated.
#0
1
A guard time (GT, CGT, or BGT) has been violated.
#1
INITD
Initial Character Detected Interrupt
4
1
read-write
0
A valid initial character has not been received.
#0
1
A valid initial character has been received.
#1
RXT
Receive Threshold Exceeded Interrupt
0
1
read-write
0
The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than or equal to the value in ET7816[RXTHRESHOLD].
#0
1
The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
#1
TXT
Transmit Threshold Exceeded Interrupt
1
1
read-write
0
The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD].
#0
1
The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD].
#1
WT
Wait Timer Interrupt
7
1
read-write
0
Wait time (WT) has not been violated.
#0
1
Wait time (WT) has been violated.
#1
MA1
UART Match Address Registers 1
0x8
8
read-write
n
0x0
0x0
MA
Match Address
0
8
read-write
MA2
UART Match Address Registers 2
0x9
8
read-write
n
0x0
0x0
MA
Match Address
0
8
read-write
S1
UART Status Register 1
0x4
8
read-only
n
0x0
0x0
FE
Framing Error Flag
1
1
read-only
0
No framing error detected.
#0
1
Framing error.
#1
IDLE
Idle Line Flag
4
1
read-only
0
Receiver input is either active now or has never become active since the IDLE flag was last cleared.
#0
1
Receiver input has become idle or the flag has not been cleared since it last asserted.
#1
NF
Noise Flag
2
1
read-only
0
No noise detected.
#0
1
Noise detected in the received character in D.
#1
OR
Receiver Overrun Flag
3
1
read-only
0
No overrun has occurred since the last time the flag was cleared.
#0
1
Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.
#1
PF
Parity Error Flag
0
1
read-only
0
No parity error detected.
#0
1
Parity error.
#1
RDRF
Receive Data Register Full Flag
5
1
read-only
0
Receive data buffer is empty.
#0
1
Receive data buffer is full.
#1
TC
Transmit Complete Flag
6
1
read-only
0
Transmitter active (sending data, a preamble, or a break).
#0
1
Transmitter idle (transmission activity complete).
#1
TDRE
Transmit Data Register Empty Flag
7
1
read-only
0
Transmit data buffer is full.
#0
1
Transmit data buffer is empty.
#1
S2
UART Status Register 2
0x5
8
read-write
n
0x0
0x0
BRK13
Break Transmit Character Length
2
1
read-write
0
Break character is 10, 11, or 12 bits long.
#0
1
Break character is 13 or 14 bits long.
#1
MSBF
Most Significant Bit First
5
1
read-write
0
LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
#0
1
MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].
#1
RAF
Receiver Active Flag
0
1
read-only
0
UART receiver idle/inactive waiting for a start bit.
#0
1
UART receiver active, RxD input not idle.
#1
RWUID
Receive Wakeup Idle Detect
3
1
read-write
0
S1[IDLE] is not set upon detection of an idle character.
#0
1
S1[IDLE] is set upon detection of an idle character.
#1
RXEDGIF
RxD Pin Active Edge Interrupt Flag
6
1
read-write
0
No active edge on the receive pin has occurred.
#0
1
An active edge on the receive pin has occurred.
#1
RXINV
Receive Data Inversion
4
1
read-write
0
Receive data is not inverted.
#0
1
Receive data is inverted.
#1
TL7816
UART 7816 Transmit Length Register
0x1F
8
read-write
n
0x0
0x0
TLEN
Transmit Length
0
8
read-write
WF7816
UART 7816 Wait FD Register
0x1D
8
read-write
n
0x0
0x0
GTFD
FD Multiplier
0
8
read-write
WGP7816_T1
UART 7816 Wait and Guard Parameter Register
0x3E
8
read-write
n
0x0
0x0
BGI
Block Guard Time Integer (C7816[TTYPE] = 1)
0
4
read-write
CWI1
Character Wait Time Integer 1 (C7816[TTYPE] = 1)
4
4
read-write
WN7816
UART 7816 Wait N Register
0x1C
8
read-write
n
0x0
0x0
GTN
Guard Band N
0
8
read-write
WP7816
UART 7816 Wait Parameter Register
0x1B
8
read-write
n
0x0
0x0
WTX
Wait Time Multiplier (C7816[TTYPE] = 1)
0
8
read-write
WP7816A_T0
UART 7816 Wait Parameter Register A
UART2
0x3C
8
read-write
n
0x0
0x0
WI_H
Wait Time Integer High (C7816[TTYPE] = 0)
0
8
read-write
WP7816A_T1
UART 7816 Wait Parameter Register A
UART2
0x3C
8
read-write
n
0x0
0x0
BWI_H
Block Wait Time Integer High (C7816[TTYPE] = 1)
0
8
read-write
WP7816B_T0
UART 7816 Wait Parameter Register B
UART2
0x3D
8
read-write
n
0x0
0x0
WI_L
Wait Time Integer Low (C7816[TTYPE] = 0)
0
8
read-write
WP7816B_T1
UART 7816 Wait Parameter Register B
UART2
0x3D
8
read-write
n
0x0
0x0
BWI_L
Block Wait Time Integer Low (C7816[TTYPE] = 1)
0
8
read-write
WP7816C_T1
UART 7816 Wait Parameter Register C
0x3F
8
read-write
n
0x0
0x0
CWI2
Character Wait Time Integer 2 (C7816[TTYPE] = 1)
0
5
read-write
USB0
Universal Serial Bus, OTG Capable Controller
USB0
0x0
0x0
0x15D
registers
n
USB0
24
ADDINFO
Peripheral Additional Info register
0xC
8
read-only
n
0x0
0x0
IEHOST
This bit is set if host mode is enabled.
0
1
read-only
ADDR
Address register
0x98
8
read-write
n
0x0
0x0
ADDR
USB Address
0
7
read-write
BDTPAGE1
BDT Page register 1
0x9C
8
read-write
n
0x0
0x0
BDTBA
Provides address bits 15 through 9 of the BDT base address.
1
7
read-write
BDTPAGE2
BDT Page Register 2
0xB0
8
read-write
n
0x0
0x0
BDTBA
Provides address bits 23 through 16 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory
0
8
read-write
BDTPAGE3
BDT Page Register 3
0xB4
8
read-write
n
0x0
0x0
BDTBA
Provides address bits 31 through 24 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory
0
8
read-write
CLK_RECOVER_CTRL
USB Clock recovery control
0x140
8
read-write
n
0x0
0x0
CLOCK_RECOVER_EN
Crystal-less USB enable
7
1
read-write
0
Disable clock recovery block (default)
#0
1
Enable clock recovery block
#1
RESET_RESUME_ROUGH_EN
Reset/resume to rough phase enable
6
1
read-write
0
Always works in tracking phase after the first time rough to track transition (default)
#0
1
Go back to rough stage whenever bus reset or bus resume occurs
#1
RESTART_IFRTRIM_EN
Restart from IFR trim value
5
1
read-write
0
Trim fine adjustment always works based on the previous updated trim fine value (default)
#0
1
Trim fine restarts from the IFR trim value whenever bus_reset/bus_resume is detected or module enable is desasserted
#1
CLK_RECOVER_INT_EN
Clock recovery combined interrupt enable
0x154
8
read-write
n
0x0
0x0
OVF_ERROR_EN
Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT.
4
1
read-write
0
The interrupt will be masked
#0
1
The interrupt will be enabled (default)
#1
CLK_RECOVER_INT_STATUS
Clock recovery separated interrupt status
0x15C
8
read-write
n
0x0
0x0
OVF_ERROR
Indicates that the USB clock recovery algorithm has detected that the frequency trim adjustment needed for the IRC48M output clock is outside the available TRIM_FINE adjustment range for the IRC48M module
4
1
read-write
0
No interrupt is reported
#0
1
Unmasked interrupt has been generated
#1
CLK_RECOVER_IRC_EN
IRC48M oscillator enable register
0x144
8
read-write
n
0x0
0x0
IRC_EN
IRC48M enable
1
1
read-write
0
Disable the IRC48M module (default)
#0
1
Enable the IRC48M module
#1
CONTROL
USB OTG Control register
0x108
8
read-write
n
0x0
0x0
DPPULLUPNONOTG
Provides control of the DP Pullup in USB, if USB is configured in non-OTG device mode.
4
1
read-write
0
DP Pullup in non-OTG device mode is not enabled.
#0
1
DP Pullup in non-OTG device mode is enabled.
#1
CTL
Control register
0x94
8
read-write
n
0x0
0x0
JSTATE
Live USB differential receiver JSTATE signal
7
1
read-write
ODDRST
Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which then specifies the EVEN BDT bank
1
1
read-write
RESUME
When set to 1 this bit enables the USB Module to execute resume signaling
2
1
read-write
SE0
Live USB Single Ended Zero signal
6
1
read-write
TXSUSPENDTOKENBUSY
In Device mode, TXD_SUSPEND is set when the SIE has disabled packet transmission and reception
5
1
read-write
USBENSOFEN
USB Enable
0
1
read-write
0
Disables the USB Module.
#0
1
Enables the USB Module.
#1
ENDPT0
Endpoint Control register
0x180
8
read-write
n
0x0
0x0
EPCTLDIS
This bit, when set, disables control (SETUP) transfers
4
1
read-write
EPHSHK
When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
0
1
read-write
EPRXEN
This bit, when set, enables the endpoint for RX transfers. See
3
1
read-write
EPSTALL
When set this bit indicates that the endpoint is stalled
1
1
read-write
EPTXEN
This bit, when set, enables the endpoint for TX transfers. See
2
1
read-write
ENDPT1
Endpoint Control register
0x244
8
read-write
n
0x0
0x0
EPCTLDIS
This bit, when set, disables control (SETUP) transfers
4
1
read-write
EPHSHK
When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
0
1
read-write
EPRXEN
This bit, when set, enables the endpoint for RX transfers. See
3
1
read-write
EPSTALL
When set this bit indicates that the endpoint is stalled
1
1
read-write
EPTXEN
This bit, when set, enables the endpoint for TX transfers. See
2
1
read-write
ENDPT10
Endpoint Control register
0x9DC
8
read-write
n
0x0
0x0
EPCTLDIS
This bit, when set, disables control (SETUP) transfers
4
1
read-write
EPHSHK
When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
0
1
read-write
EPRXEN
This bit, when set, enables the endpoint for RX transfers. See
3
1
read-write
EPSTALL
When set this bit indicates that the endpoint is stalled
1
1
read-write
EPTXEN
This bit, when set, enables the endpoint for TX transfers. See
2
1
read-write
ENDPT11
Endpoint Control register
0xAC8
8
read-write
n
0x0
0x0
EPCTLDIS
This bit, when set, disables control (SETUP) transfers
4
1
read-write
EPHSHK
When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
0
1
read-write
EPRXEN
This bit, when set, enables the endpoint for RX transfers. See
3
1
read-write
EPSTALL
When set this bit indicates that the endpoint is stalled
1
1
read-write
EPTXEN
This bit, when set, enables the endpoint for TX transfers. See
2
1
read-write
ENDPT12
Endpoint Control register
0xBB8
8
read-write
n
0x0
0x0
EPCTLDIS
This bit, when set, disables control (SETUP) transfers
4
1
read-write
EPHSHK
When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
0
1
read-write
EPRXEN
This bit, when set, enables the endpoint for RX transfers. See
3
1
read-write
EPSTALL
When set this bit indicates that the endpoint is stalled
1
1
read-write
EPTXEN
This bit, when set, enables the endpoint for TX transfers. See
2
1
read-write
ENDPT13
Endpoint Control register
0xCAC
8
read-write
n
0x0
0x0
EPCTLDIS
This bit, when set, disables control (SETUP) transfers
4
1
read-write
EPHSHK
When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
0
1
read-write
EPRXEN
This bit, when set, enables the endpoint for RX transfers. See
3
1
read-write
EPSTALL
When set this bit indicates that the endpoint is stalled
1
1
read-write
EPTXEN
This bit, when set, enables the endpoint for TX transfers. See
2
1
read-write
ENDPT14
Endpoint Control register
0xDA4
8
read-write
n
0x0
0x0
EPCTLDIS
This bit, when set, disables control (SETUP) transfers
4
1
read-write
EPHSHK
When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
0
1
read-write
EPRXEN
This bit, when set, enables the endpoint for RX transfers. See
3
1
read-write
EPSTALL
When set this bit indicates that the endpoint is stalled
1
1
read-write
EPTXEN
This bit, when set, enables the endpoint for TX transfers. See
2
1
read-write
ENDPT15
Endpoint Control register
0xEA0
8
read-write
n
0x0
0x0
EPCTLDIS
This bit, when set, disables control (SETUP) transfers
4
1
read-write
EPHSHK
When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
0
1
read-write
EPRXEN
This bit, when set, enables the endpoint for RX transfers. See
3
1
read-write
EPSTALL
When set this bit indicates that the endpoint is stalled
1
1
read-write
EPTXEN
This bit, when set, enables the endpoint for TX transfers. See
2
1
read-write
ENDPT2
Endpoint Control register
0x30C
8
read-write
n
0x0
0x0
EPCTLDIS
This bit, when set, disables control (SETUP) transfers
4
1
read-write
EPHSHK
When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
0
1
read-write
EPRXEN
This bit, when set, enables the endpoint for RX transfers. See
3
1
read-write
EPSTALL
When set this bit indicates that the endpoint is stalled
1
1
read-write
EPTXEN
This bit, when set, enables the endpoint for TX transfers. See
2
1
read-write
ENDPT3
Endpoint Control register
0x3D8
8
read-write
n
0x0
0x0
EPCTLDIS
This bit, when set, disables control (SETUP) transfers
4
1
read-write
EPHSHK
When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
0
1
read-write
EPRXEN
This bit, when set, enables the endpoint for RX transfers. See
3
1
read-write
EPSTALL
When set this bit indicates that the endpoint is stalled
1
1
read-write
EPTXEN
This bit, when set, enables the endpoint for TX transfers. See
2
1
read-write
ENDPT4
Endpoint Control register
0x4A8
8
read-write
n
0x0
0x0
EPCTLDIS
This bit, when set, disables control (SETUP) transfers
4
1
read-write
EPHSHK
When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
0
1
read-write
EPRXEN
This bit, when set, enables the endpoint for RX transfers. See
3
1
read-write
EPSTALL
When set this bit indicates that the endpoint is stalled
1
1
read-write
EPTXEN
This bit, when set, enables the endpoint for TX transfers. See
2
1
read-write
ENDPT5
Endpoint Control register
0x57C
8
read-write
n
0x0
0x0
EPCTLDIS
This bit, when set, disables control (SETUP) transfers
4
1
read-write
EPHSHK
When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
0
1
read-write
EPRXEN
This bit, when set, enables the endpoint for RX transfers. See
3
1
read-write
EPSTALL
When set this bit indicates that the endpoint is stalled
1
1
read-write
EPTXEN
This bit, when set, enables the endpoint for TX transfers. See
2
1
read-write
ENDPT6
Endpoint Control register
0x654
8
read-write
n
0x0
0x0
EPCTLDIS
This bit, when set, disables control (SETUP) transfers
4
1
read-write
EPHSHK
When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
0
1
read-write
EPRXEN
This bit, when set, enables the endpoint for RX transfers. See
3
1
read-write
EPSTALL
When set this bit indicates that the endpoint is stalled
1
1
read-write
EPTXEN
This bit, when set, enables the endpoint for TX transfers. See
2
1
read-write
ENDPT7
Endpoint Control register
0x730
8
read-write
n
0x0
0x0
EPCTLDIS
This bit, when set, disables control (SETUP) transfers
4
1
read-write
EPHSHK
When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
0
1
read-write
EPRXEN
This bit, when set, enables the endpoint for RX transfers. See
3
1
read-write
EPSTALL
When set this bit indicates that the endpoint is stalled
1
1
read-write
EPTXEN
This bit, when set, enables the endpoint for TX transfers. See
2
1
read-write
ENDPT8
Endpoint Control register
0x810
8
read-write
n
0x0
0x0
EPCTLDIS
This bit, when set, disables control (SETUP) transfers
4
1
read-write
EPHSHK
When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
0
1
read-write
EPRXEN
This bit, when set, enables the endpoint for RX transfers. See
3
1
read-write
EPSTALL
When set this bit indicates that the endpoint is stalled
1
1
read-write
EPTXEN
This bit, when set, enables the endpoint for TX transfers. See
2
1
read-write
ENDPT9
Endpoint Control register
0x8F4
8
read-write
n
0x0
0x0
EPCTLDIS
This bit, when set, disables control (SETUP) transfers
4
1
read-write
EPHSHK
When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
0
1
read-write
EPRXEN
This bit, when set, enables the endpoint for RX transfers. See
3
1
read-write
EPSTALL
When set this bit indicates that the endpoint is stalled
1
1
read-write
EPTXEN
This bit, when set, enables the endpoint for TX transfers. See
2
1
read-write
ERREN
Error Interrupt Enable register
0x8C
8
read-write
n
0x0
0x0
BTOERREN
BTOERR Interrupt Enable
4
1
read-write
0
Disables the BTOERR interrupt.
#0
1
Enables the BTOERR interrupt.
#1
BTSERREN
BTSERR Interrupt Enable
7
1
read-write
0
Disables the BTSERR interrupt.
#0
1
Enables the BTSERR interrupt.
#1
CRC16EN
CRC16 Interrupt Enable
2
1
read-write
0
Disables the CRC16 interrupt.
#0
1
Enables the CRC16 interrupt.
#1
CRC5EOFEN
CRC5/EOF Interrupt Enable
1
1
read-write
0
Disables the CRC5/EOF interrupt.
#0
1
Enables the CRC5/EOF interrupt.
#1
DFN8EN
DFN8 Interrupt Enable
3
1
read-write
0
Disables the DFN8 interrupt.
#0
1
Enables the DFN8 interrupt.
#1
DMAERREN
DMAERR Interrupt Enable
5
1
read-write
0
Disables the DMAERR interrupt.
#0
1
Enables the DMAERR interrupt.
#1
PIDERREN
PIDERR Interrupt Enable
0
1
read-write
0
Disables the PIDERR interrupt.
#0
1
Enters the PIDERR interrupt.
#1
ERRSTAT
Error Interrupt Status register
0x88
8
read-write
n
0x0
0x0
BTOERR
This bit is set when a bus turnaround timeout error occurs
4
1
read-write
BTSERR
This bit is set when a bit stuff error is detected
7
1
read-write
CRC16
This bit is set when a data packet is rejected due to a CRC16 error.
2
1
read-write
CRC5
This error interrupt has two functions
1
1
read-write
DFN8
This bit is set if the data field received was not 8 bits in length
3
1
read-write
DMAERR
This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given the bus before it needs to receive or transmit data
5
1
read-write
PIDERR
This bit is set when the PID check field fails.
0
1
read-write
FRMNUMH
Frame Number register High
0xA4
8
read-write
n
0x0
0x0
FRM
This 3-bit field and the 8-bit field in the Frame Number Register Low are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory
0
3
read-write
FRMNUML
Frame Number register Low
0xA0
8
read-write
n
0x0
0x0
FRM
This 8-bit field and the 3-bit field in the Frame Number Register High are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory
0
8
read-write
IDCOMP
Peripheral ID Complement register
0x4
8
read-only
n
0x0
0x0
NID
Ones' complement of PERID[ID]. bits.
0
6
read-only
INTEN
Interrupt Enable register
0x84
8
read-write
n
0x0
0x0
ERROREN
ERROR Interrupt Enable
1
1
read-write
0
Disables the ERROR interrupt.
#0
1
Enables the ERROR interrupt.
#1
RESUMEEN
RESUME Interrupt Enable
5
1
read-write
0
Disables the RESUME interrupt.
#0
1
Enables the RESUME interrupt.
#1
SLEEPEN
SLEEP Interrupt Enable
4
1
read-write
0
Disables the SLEEP interrupt.
#0
1
Enables the SLEEP interrupt.
#1
SOFTOKEN
SOFTOK Interrupt Enable
2
1
read-write
0
Disbles the SOFTOK interrupt.
#0
1
Enables the SOFTOK interrupt.
#1
STALLEN
STALL Interrupt Enable
7
1
read-write
0
Diasbles the STALL interrupt.
#0
1
Enables the STALL interrupt.
#1
TOKDNEEN
TOKDNE Interrupt Enable
3
1
read-write
0
Disables the TOKDNE interrupt.
#0
1
Enables the TOKDNE interrupt.
#1
USBRSTEN
USBRST Interrupt Enable
0
1
read-write
0
Disables the USBRST interrupt.
#0
1
Enables the USBRST interrupt.
#1
ISTAT
Interrupt Status register
0x80
8
read-write
n
0x0
0x0
ERROR
This bit is set when any of the error conditions within Error Interrupt Status (ERRSTAT) register occur
1
1
read-write
RESUME
This bit is set when a K-state is observed on the DP/DM signals for 2
5
1
read-write
SLEEP
This bit is set when the USB Module detects a constant idle on the USB bus for 3 ms
4
1
read-write
SOFTOK
This bit is set when the USB Module receives a Start Of Frame (SOF) token.
2
1
read-write
STALL
Stall Interrupt
7
1
read-write
TOKDNE
This bit is set when the current token being processed has completed
3
1
read-write
USBRST
This bit is set when the USB Module has decoded a valid USB reset
0
1
read-write
OBSERVE
USB OTG Observe register
0x104
8
read-only
n
0x0
0x0
DMPD
Provides observability of the D- Pulldown signal output from USB.
4
1
read-only
0
D- pulldown disabled.
#0
1
D- pulldown enabled.
#1
DPPD
Provides observability of the D+ Pulldown signal output from USB.
6
1
read-only
0
D+ pulldown disabled.
#0
1
D+ pulldown enabled.
#1
DPPU
Provides observability of the D+ Pullup signal output from USB .
7
1
read-only
0
D+ pullup disabled.
#0
1
D+ pullup enabled.
#1
PERID
Peripheral ID register
0x0
8
read-only
n
0x0
0x0
ID
Peripheral Identification
0
6
read-only
REV
Peripheral Revision register
0x8
8
read-only
n
0x0
0x0
REV
Revision
0
8
read-only
STAT
Status register
0x90
8
read-only
n
0x0
0x0
ENDP
This four-bit field encodes the endpoint address that received or transmitted the previous token
4
4
read-only
ODD
This bit is set if the last buffer descriptor updated was in the odd bank of the BDT.
2
1
read-only
TX
Transmit Indicator
3
1
read-only
0
The most recent transaction was a receive operation.
#0
1
The most recent transaction was a transmit operation.
#1
USBCTRL
USB Control register
0x100
8
read-write
n
0x0
0x0
PDE
Enables the weak pulldowns on the USB transceiver.
6
1
read-write
0
Weak pulldowns are disabled on D+ and D-.
#0
1
Weak pulldowns are enabled on D+ and D-.
#1
SUSP
Places the USB transceiver into the suspend state.
7
1
read-write
0
USB transceiver is not in suspend state.
#0
1
USB transceiver is in suspend state.
#1
USBFRMADJUST
Frame Adjust Register
0x114
8
read-write
n
0x0
0x0
ADJ
Frame Adjustment
0
8
read-write
USBTRC0
USB Transceiver Control register 0
0x10C
8
read-write
n
0x0
0x0
SYNC_DET
Synchronous USB Interrupt Detect
1
1
read-only
0
Synchronous interrupt has not been detected.
#0
1
Synchronous interrupt has been detected.
#1
USBRESET
USB Reset
7
1
write-only
0
Normal USB module operation.
#0
1
Returns the USB module to its reset state.
#1
USBRESMEN
Asynchronous Resume Interrupt Enable
5
1
read-write
0
USB asynchronous wakeup from suspend mode disabled.
#0
1
USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs from the synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered state of the D+ and D- pins. This interrupt should only be enabled when the Transceiver is suspended.
#1
USB_CLK_RECOVERY_INT
Combined USB Clock Recovery interrupt status
2
1
read-only
USB_RESUME_INT
USB Asynchronous Interrupt
0
1
read-only
0
No interrupt was generated.
#0
1
Interrupt was generated because of the USB asynchronous interrupt.
#1
VREF
Voltage Reference
VREF
0x0
0x0
0x2
registers
n
SC
VREF Status and Control Register
0x1
8
read-write
n
0x0
0x0
ICOMPEN
Second order curvature compensation enable
5
1
read-write
0
Disabled
#0
1
Enabled
#1
MODE_LV
Buffer Mode selection
0
2
read-write
00
Bandgap on only, for stabilization and startup
#00
01
High power buffer mode enabled
#01
10
Low-power buffer mode enabled
#10
REGEN
Regulator enable
6
1
read-write
0
Internal 1.75 V regulator is disabled.
#0
1
Internal 1.75 V regulator is enabled.
#1
VREFEN
Internal Voltage Reference enable
7
1
read-write
0
The module is disabled.
#0
1
The module is enabled.
#1
VREFST
Internal Voltage Reference stable
2
1
read-only
0
The module is disabled or not stable.
#0
1
The module is stable.
#1
TRM
VREF Trim Register
0x0
8
read-write
n
0x0
0x0
CHOPEN
Chop oscillator enable. When set, internal chopping operation is enabled and the internal analog offset will be minimized.
6
1
read-write
0
Chop oscillator is disabled.
#0
1
Chop oscillator is enabled.
#1
TRIM
Trim bits
0
6
read-write
000000
Min
#0
111111
Max
#111111